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/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dvstrldr_sys.s24 vstr fpscr, [r0] label
148 vstr fpcxts, [sp], #-24 label
188 vstr fpcxtns, [r0] label
284 vstr vpr, [r6, #500] label
292 vstr p0, [lr, #-508] label
300 vstr vpr, [r6, #500]! label
308 vstr p0, [lr, #-508]! label
316 vstr vpr, [r6], #500 label
324 vstr p0, [lr], #-508 label
332 vstr p0, [sp], #-24 label
[all …]
H A Dsimple-fp-encoding.s281 @ CHECK: vstr d4, [r1] @ encoding: [0x00,0x4b,0x81,0xed]
282 @ CHECK: vstr d4, [r1, #24] @ encoding: [0x06,0x4b,0x81,0xed]
283 @ CHECK: vstr d4, [r1, #-24] @ encoding: [0x06,0x4b,0x01,0xed]
287 vstr.64 d4, [r1]
288 vstr.64 d4, [r1, #24]
289 vstr.64 d4, [r1, #-24]
290 vstr s0, [lr]
291 vstr d0, [lr] define
296 vstr.32 s4, [r1]
297 vstr.32 s4, [r1, #24]
[all …]
H A Dmve-fp-registers.s112 vstr.16 s0, [r0]
113 # FP16: vstr.16 s0, [r0] @ encoding: [0x80,0xed,0x00,0x09]
116 vstr s0, [r0] label
117 # FP32: vstr s0, [r0] @ encoding: [0x80,0xed,0x00,0x0a]
120 vstr d0, [r0] define
121 # FP32: vstr d0, [r0] @ encoding: [0x80,0xed,0x00,0x0b]
H A Dfullfp16.s258 vstr.16 s1, [pc, #6]
259 vstr.16 s2, [pc, #510]
260 vstr.16 s3, [pc, #-510]
261 vstr.16 s4, [r4, #-18]
262 @ ARM: vstr.16 s1, [pc, #6] @ encoding: [0x03,0x09,0xcf,0xed]
263 @ ARM: vstr.16 s2, [pc, #510] @ encoding: [0xff,0x19,0x8f,0xed]
264 @ ARM: vstr.16 s3, [pc, #-510] @ encoding: [0xff,0x19,0x4f,0xed]
265 @ ARM: vstr.16 s4, [r4, #-18] @ encoding: [0x09,0x29,0x04,0xed]
266 @ THUMB: vstr.16 s1, [pc, #6] @ encoding: [0xcf,0xed,0x03,0x09]
267 @ THUMB: vstr.16 s2, [pc, #510] @ encoding: [0x8f,0xed,0xff,0x19]
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dvstrldr_sys.txt17 # CHECK-NOSEC: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
18 # CHECK-NOMVE: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
19 # CHECK-NOVFP: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
20 # CHECK: vstr fpscr, [r0] @ encoding: [0x80,0xed,0x80,0x2f]
146 # CHECK: vstr fpcxtns, [r0] @ encoding: [0xc0,0xed,0x80,0xcf]
218 # CHECK: vstr vpr, [r6, #500] @ encoding: [0xc6,0xed,0xfd,0x8f]
224 # CHECK: vstr p0, [lr, #-508] @ encoding: [0x4e,0xed,0xff,0xaf]
230 # CHECK: vstr vpr, [r6, #500]! @ encoding: [0xe6,0xed,0xfd,0x8f]
242 # CHECK: vstr vpr, [r6], #500 @ encoding: [0xe6,0xec,0xfd,0x8f]
248 # CHECK: vstr p0, [lr], #-508 @ encoding: [0x6e,0xec,0xff,0xaf]
[all …]
H A Dfp-encoding.txt193 # CHECK: vstr d4, [r1]
194 # CHECK: vstr d4, [r1, #24]
195 # CHECK: vstr d4, [r1, #-24]
200 # CHECK: vstr s4, [r1]
201 # CHECK: vstr s4, [r1, #24]
202 # CHECK: vstr s4, [r1, #-24]
H A Dfullfp16-arm.txt171 # CHECK: vstr.16 s1, [pc, #6]
172 # CHECK: vstr.16 s2, [pc, #510]
173 # CHECK: vstr.16 s3, [pc, #-510]
174 # CHECK: vstr.16 s4, [r4, #-18]
H A Dfullfp16-thumb.txt171 # CHECK: vstr.16 s1, [pc, #6]
172 # CHECK: vstr.16 s2, [pc, #510]
173 # CHECK: vstr.16 s3, [pc, #-510]
174 # CHECK: vstr.16 s4, [r4, #-18]
/llvm-project-15.0.7/libc/AOR_v20.02/string/arm/
H A Dmemcpy.S254 vstr d0, [dst, #0] define
256 vstr d1, [dst, #8] define
258 vstr d0, [dst, #16] define
260 vstr d1, [dst, #24] define
262 vstr d0, [dst, #32] define
264 vstr d1, [dst, #40] define
266 vstr d0, [dst, #48] define
268 vstr d1, [dst, #56] define
282 vstr d0, [dst, #-56] define
294 vstr d0, [dst, #-8] define
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-fusedMAC.ll14 ; CHECK-NEXT: vstr.16 s4, [r0]
24 ; DONT-FUSE-NEXT: vstr.16 s0, [r0]
43 ; CHECK-NEXT: vstr.16 s4, [r0]
72 ; CHECK-NEXT: vstr.16 s4, [r0]
102 ; CHECK-NEXT: vstr.16 s4, [r0]
131 ; CHECK-NEXT: vstr.16 s4, [r0]
158 ; CHECK-NEXT: vstr.16 s4, [r0]
185 ; CHECK-NEXT: vstr.16 s0, [r0]
210 ; CHECK-NEXT: vstr.16 s2, [r0]
236 ; CHECK-NEXT: vstr.16 s4, [r0]
[all …]
H A Dfp16-fullfp16.ll9 ; CHECK-NEXT: vstr.16 s0, [r0]
23 ; CHECK-NEXT: vstr.16 s0, [r0]
37 ; CHECK-NEXT: vstr.16 s0, [r0]
51 ; CHECK-NEXT: vstr.16 s0, [r0]
71 ; CHECK-NEXT: vstr.16 s0, [r4]
83 ; CHECK-NEXT: vstr.16 s0, [r1]
130 ; CHECK-NEXT: vstr.16 s0, [r1]
141 ; CHECK-NEXT: vstr.16 s0, [r1]
165 ; CHECK-NEXT: vstr.16 s0, [r0]
175 ; CHECK-NEXT: vstr.16 s0, [r0]
[all …]
H A Dfp16-load-store.ll59 ; CHECK: vstr.16 {{s[0-9]+}}, [r1]
69 ; CHECK: vstr.16 {{s[0-9]+}}, [r1, #510]
80 ; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
90 ; CHECK: vstr.16 {{s[0-9]+}}, [r1, #-510]
101 ; CHECK: vstr.16 {{s[0-9]+}}, [[[ADDR]]]
H A Dvsel-fp16.ll15 ; CHECK-NEXT: vstr.16 s0, [r0]
34 ; CHECK-NEXT: vstr.16 s0, [r0]
53 ; CHECK-NEXT: vstr.16 s0, [r0]
72 ; CHECK-NEXT: vstr.16 s0, [r0]
91 ; CHECK-NEXT: vstr.16 s0, [r0]
113 ; CHECK-NEXT: vstr.16 s0, [r0]
137 ; CHECK-NEXT: vstr.16 s0, [r0]
161 ; CHECK-NEXT: vstr.16 s0, [r0]
185 ; CHECK-NEXT: vstr.16 s0, [r0]
209 ; CHECK-NEXT: vstr.16 s0, [r0]
[all …]
H A Dsubreg-remat.ll17 ; CHECK: vstr d0,
21 ; CHECK: vstr [[D16]], [r1]
42 ; CHECK-NOT: vstr
46 ; CHECK: vstr [[D0:d[0-9]+]], [r0]
H A Dcmse-cve-2021-35465-return.ll46 ; CHECK-8M-FP-CVE-2021-35465-NEXT: vstr d3, [sp, #24]
48 ; CHECK-8M-FP-CVE-2021-35465-NEXT: vstr d4, [sp, #32]
50 ; CHECK-8M-FP-CVE-2021-35465-NEXT: vstr d5, [sp, #40]
51 ; CHECK-8M-FP-CVE-2021-35465-NEXT: vstr d6, [sp, #48]
52 ; CHECK-8M-FP-CVE-2021-35465-NEXT: vstr d7, [sp, #56]
H A Dbfloat.ll27 ; HARD-NEXT: vstr.16 s0, [r0]
33 ; SOFT-NEXT: vstr.16 s0, [r1]
59 ; HARD-NEXT: vstr d0, [r0]
H A DlowerMUL-newload.ll30 ; CHECK-NEXT: vstr d16, [r0, #16]
80 ; CHECK-NEXT: vstr d16, [r0, #16]
114 ; CHECK-NEXT: vstr d19, [r0, #16]
120 ; CHECK-NEXT: vstr d16, [r1, #16]
124 ; CHECK-NEXT: vstr d16, [r0, #16]
184 ; CHECK-NEXT: vstr d18, [r0, #16]
192 ; CHECK-NEXT: vstr d16, [r1, #16]
199 ; CHECK-NEXT: vstr d16, [r0, #16]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dinflate-regs.ll10 ; CHECK-NOT: vstr
12 ; CHECK-NOT: vstr
14 ; CHECK: vstr s
29 ; CHECK-NOT: vstr
31 ; CHECK-NOT: vstr
33 ; CHECK: vstr s
H A Dmve-gatherscatter-mmo.ll70 …call void @llvm.arm.mve.vstr.scatter.offset.p0i8.v4i32.v4i32(i8* %base, <4 x i32> %offset, <4 x i3…
88 call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 -472, <2 x i64> %value)
98 …call void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v2i1(<2 x i64> %addr, i32 888, <2…
107 …%1 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64> %0, i32 208, <2 x i64…
119 …%3 = call <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.predicated.v2i64.v2i64.v2i1(<2 x i64> %0, i…
133 declare void @llvm.arm.mve.vstr.scatter.offset.p0i8.v4i32.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)
134 declare void @llvm.arm.mve.vstr.scatter.offset.predicated.p0i8.v16i8.v16i8.v16i1(i8*, <16 x i8>, <1…
135 declare void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)
136 declare void @llvm.arm.mve.vstr.scatter.base.predicated.v2i64.v2i64.v2i1(<2 x i64>, i32, <2 x i64>,…
137 declare <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)
[all …]
H A Dmve-extractstore.ll13 ; CHECK-NEXT: vstr.16 s0, [r0]
30 ; CHECK-NEXT: vstr.16 s2, [r0]
44 ; CHECK-NEXT: vstr.16 s0, [r0]
57 ; CHECK-NEXT: vstr.16 s2, [r0]
107 ; CHECK-NEXT: vstr s1, [r1]
124 ; CHECK-NEXT: vstr s2, [r1]
137 ; CHECK-NEXT: vstr s1, [r0]
151 ; CHECK-NEXT: vstr s2, [r0]
164 ; CHECK-NEXT: vstr s5, [r0]
180 ; CHECK-NEXT: vstr s6, [r0]
H A Dmve-scatter-ptrs.ll129 ; CHECK-NEXT: vstr s0, [r1]
130 ; CHECK-NEXT: vstr s1, [r0]
163 ; CHECK-NEXT: vstr s0, [r1]
164 ; CHECK-NEXT: vstr s1, [lr]
165 ; CHECK-NEXT: vstr s2, [r3]
166 ; CHECK-NEXT: vstr s3, [r12]
167 ; CHECK-NEXT: vstr s4, [r0]
168 ; CHECK-NEXT: vstr s5, [r2]
169 ; CHECK-NEXT: vstr s6, [r4]
170 ; CHECK-NEXT: vstr s7, [r5]
[all …]
H A Dmve-scatter-ind16-unscaled.ll117 ; CHECK-NEXT: vstr.16 s0, [r1]
119 ; CHECK-NEXT: vstr.16 s0, [r2]
122 ; CHECK-NEXT: vstr.16 s1, [r1]
123 ; CHECK-NEXT: vstr.16 s0, [r2]
126 ; CHECK-NEXT: vstr.16 s2, [r0]
127 ; CHECK-NEXT: vstr.16 s0, [r1]
130 ; CHECK-NEXT: vstr.16 s3, [r0]
131 ; CHECK-NEXT: vstr.16 s0, [r1]
190 ; CHECK-NEXT: vstr.16 s0, [r1]
192 ; CHECK-NEXT: vstr.16 s0, [r2]
[all …]
H A Dmve-pred-spill.ll32 ; CHECK-LE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
62 ; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
90 ; CHECK-LE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
111 ; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
142 ; CHECK-LE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
164 ; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
195 ; CHECK-LE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
217 ; CHECK-BE-NEXT: vstr p0, [sp, #4] @ 4-byte Spill
H A Dmve-masked-store.ll739 ; CHECK-LE-NEXT: vstr.16 s0, [sp, #8]
745 ; CHECK-LE-NEXT: vstr.16 s3, [sp, #4]
752 ; CHECK-LE-NEXT: vstr.16 s0, [sp]
852 ; CHECK-BE-NEXT: vstr.16 s0, [sp, #8]
865 ; CHECK-BE-NEXT: vstr.16 s0, [sp]
1238 ; CHECK-LE-NEXT: vstr.16 s4, [r0]
1297 ; CHECK-BE-NEXT: vstr.16 s0, [r0]
1362 ; CHECK-LE-NEXT: vstr.16 s4, [r0]
1421 ; CHECK-BE-NEXT: vstr.16 s0, [r0]
1506 ; CHECK-LE-NEXT: vstr.16 s0, [sp]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/
H A Dscatter-gather.ll1157 declare void @llvm.arm.mve.vstr.scatter.offset.p0i8.v8i16.v8i16(i8*, <8 x i16>, <8 x i16>, i32, i32)
1169 declare void @llvm.arm.mve.vstr.scatter.offset.p0i8.v4i32.v4i32(i8*, <4 x i32>, <4 x i32>, i32, i32)
1249 call void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64> %addr, i32 408, <2 x i64> %value)
1253 declare void @llvm.arm.mve.vstr.scatter.base.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)
1317 declare <2 x i64> @llvm.arm.mve.vstr.scatter.base.wb.v2i64.v2i64(<2 x i64>, i32, <2 x i64>)
1695 declare void @llvm.arm.mve.vstr.scatter.base.v4i32.v4f32(<4 x i32>, i32, <4 x float>)
1749 call void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32> %addr, i32 156, <4 x i32> %value)
1753 declare void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32>, i32, <4 x i32>)
1761 call void @llvm.arm.mve.vstr.scatter.base.v4i32.v4i32(<4 x i32> %addr, i32 212, <4 x i32> %value)
1779 declare <4 x i32> @llvm.arm.mve.vstr.scatter.base.wb.v4i32.v4f32(<4 x i32>, i32, <4 x float>)
[all …]

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