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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dschedule-fs-loop-nested.ll35 %temp4.0 = phi float [ %tmp22, %main_body ], [ %temp4.1, %IF31 ]
46 %max.0.i = call float @llvm.maxnum.f32(float %temp4.0, float 0.000000e+00)
60 %temp6.1 = phi float [ %temp4.1, %ENDIF30 ], [ %temp6.0, %LOOP ]
62 %temp4.1 = phi float [ %temp5.1, %ENDIF30 ], [ %temp4.0, %LOOP ]
H A Dr600cfg.ll21 %temp4.1 = phi float [ %., %main_body ], [ %52, %LOOP47 ]
22 %10 = bitcast float %temp4.1 to i32
62 %39 = bitcast float %temp4.1 to i32
71 %48 = bitcast float %temp4.1 to i32
H A Dschedule-vs-if-nested-loop.ll101 %temp4.0 = phi float [ %97, %ENDIF19 ], [ -2.000000e+00, %main_body ]
102 %79 = fcmp uge float %temp4.0, %0
112 %86 = fcmp une float %2, %temp4.0
126 %97 = fadd float %temp4.0, 1.000000e+00
H A Dschedule-vs-if-nested-loop-failure.ll116 %temp4.0 = phi float [ %105, %Flow ], [ -2.000000e+00, %main_body ]
117 %85 = fcmp uge float %temp4.0, %0
128 %93 = fcmp une float %1, %temp4.0
156 %115 = fadd float %temp4.0, 1.000000e+00
H A Dschedule-if-2.ll61 %temp4.0 = phi float [ %2, %IF ], [ %56, %IF23 ], [ 0.000000e+00, %ELSE ]
65 %44 = insertelement <4 x float> undef, float %temp4.0, i32 0
H A Dsgpr-copy.ll127 %temp4.0 = phi float [ %tmp83, %IF ], [ %tmp31, %main_body ]
148 %tmp97 = fmul float %tmp28, %temp4.0
149 %tmp98 = fmul float %tmp29, %temp4.0
150 %tmp99 = fmul float %tmp30, %temp4.0
186 %temp4.0 = phi float [ %tmp21, %main_body ], [ %temp5.0, %ENDIF ]
188 %temp6.0 = phi float [ %tmp23, %main_body ], [ %temp4.0, %ENDIF ]
199 …call void @llvm.amdgcn.exp.f32(i32 0, i32 15, float %temp4.0, float %temp5.0, float %temp6.0, floa…
294 %temp4.7 = phi float [ 0.000000e+00, %entry ], [ %v, %ENDIF69 ]
297 %l = bitcast float %temp4.7 to i32
H A Dwqm.ll3010 %temp4 = call float @llvm.amdgcn.strict.wwm.f32(float %reload_wwm)
3011 %temp5 = fadd float %temp3, %temp4
3120 %temp4 = call float @llvm.amdgcn.strict.wqm.f32(float %reload_wwm)
3121 %temp5 = fadd float %temp3, %temp4
3226 %temp4 = fadd float %temp2, %temp3
3227 …%tex2 = call float @llvm.amdgcn.image.sample.1d.f32.f32(i32 1, float %temp4, <8 x i32> %res2, <4 x…
/llvm-project-15.0.7/llvm/test/Transforms/StructurizeCFG/
H A Dnested-loop-order.ll15 %temp4.0.ph = phi i32 [ 0, %main_body ], [ %tmp20, %ENDIF28 ]
21 %temp4.0 = phi i32 [ %temp4.0.ph, %LOOP.outer ], [ %tmp20, %IF29 ]
22 %tmp20 = add i32 %temp4.0, 1
/llvm-project-15.0.7/llvm/test/Transforms/ArgumentPromotion/
H A Dbyval.ll110 %temp4 = getelementptr %struct.ss, %struct.ss* %c, i32 0, i32 1
111 %temp5 = load i64, i64* %temp4, align 8
113 store i64 %temp6, i64* %temp4, align 8
153 %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
154 store i64 2, i64* %temp4, align 4
H A Dpr42028-recursion.ll39 %temp4 = load %S*, %S** %temp3
40 %temp5 = call i32 @test_inf_promote_callee2(%S* %temp4, %S* %temp2)
H A Dbyval-2.ll44 %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
45 store i64 2, i64* %temp4, align 4
H A Dattrs.ll43 %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
44 store i64 2, i64* %temp4, align 4
H A Dcrash.ll93 %temp4 = load %S*, %S** %temp3
94 %temp5 = call i32 @test_inf_promote_callee(%S* %temp4, %S* %temp2)
H A Dstore-into-inself.ll94 %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
95 store i64 2, i64* %temp4, align 8
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Ddce-after-argument-promotion.ll39 %temp4 = getelementptr %struct.ss, %struct.ss* %S, i32 0, i32 1
40 store i64 2, i64* %temp4, align 4
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dtype_visibility.cpp90 namespace temp4 { namespace
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dmatmul.ll78 %temp4 = load double, double* %arrayidx13.i, align 8
79 %mul14.i = fmul double %temp, %temp4
105 %mul62.i = fmul double %temp4, %temp10
/llvm-project-15.0.7/llvm/test/CodeGen/X86/AMX/
H A Damx-configO0toO0.ll670 %indirect-arg-temp4.i79 = alloca <256 x i32>, align 1024
702 %indirect-arg-temp4.i = alloca <256 x i32>, align 1024
914 store <256 x i32> %88, ptr %indirect-arg-temp4.i, align 1024
917 … void @llvm.memcpy.p0.p0.i64(ptr align 1 %indirect-arg-temp4.i79, ptr align 1 %indirect-arg-temp4.…
920 %src1.i = load <256 x i32>, ptr %indirect-arg-temp4.i79, align 1024
/llvm-project-15.0.7/llvm/test/Transforms/DeadStoreElimination/
H A Dnoop-stores.ll48 %temp4 = getelementptr { i32, i32 }, { i32, i32 }* %x, i32 0, i32 0
49 %temp5 = load i32, i32* %temp4, align 4
53 store i32 %temp5, i32* %temp4, align 4
/llvm-project-15.0.7/openmp/runtime/src/
H A Dkmp_dispatch_hier.h96 kmp_int64 temp4 = large_chunks[i]; in sort() local
104 large_chunks[switch_index] = temp4; in sort()