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/llvm-project-15.0.7/polly/lib/External/isl/imath/examples/
H A Dimcalc.c559 if (sp->used >= sp->alloc) { in stack_push()
575 sp->elts[sp->used++] = elt; in stack_push()
585 mp_int_clear(sp->elts[sp->used]); in stack_pop()
586 sp->elts[sp->used] = NULL; in stack_pop()
605 if (sp->mused >= sp->mslots) { in mem_insert()
993 sp->elts[sp->used - 1] = sp->elts[sp->used - 2]; in cf_swap()
994 sp->elts[sp->used - 2] = t; in cf_swap()
1002 sp->elts[sp->used - 3] = sp->elts[sp->used - 2]; in cf_rot()
1003 sp->elts[sp->used - 2] = sp->elts[sp->used - 1]; in cf_rot()
1004 sp->elts[sp->used - 1] = t; in cf_rot()
[all …]
/llvm-project-15.0.7/llvm/test/MC/AArch64/
H A Dseh-packed-unwind.s333 sub sp, sp, #16
338 add sp, sp, #16
372 sub sp, sp, #0
377 add sp, sp, #0
416 sub sp, sp, #32
421 add sp, sp, #32
441 sub sp, sp, #32
847 sub sp, sp, #32
860 add sp, sp, #32
919 sub sp, sp, #16
[all …]
H A Darmv8.1a-lse.s14 cas w2, w3, [sp]
16 casa w2, w3, [sp]
18 casl w2, w3, [sp]
20 casal w2, w3, [sp]
31 casb w2, w3, [sp]
33 cash w2, w3, [sp]
35 casab w2, w3, [sp]
37 caslb w2, w3, [sp]
65 cas x2, x3, [sp]
67 casa x2, x3, [sp]
[all …]
H A Dseh-packed-epilog.s101 sub sp, sp, #48
137 add sp, sp, #48
147 sub sp, sp, #48
156 add sp, sp, #48
165 sub sp, sp, #48
171 add sp, sp, #48
183 sub sp, sp, #48
185 sub sp, sp, #32
192 add sp, sp, #16
194 add sp, sp, #48
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/M68k/
H A DCollapseMOVEM.mir17 MOVM32mp 1, 0, $sp
18 MOVM32mp 2, 4, $sp
19 MOVM32mp 4, 8, $sp
20 MOVM32mp 128, 12, $sp
21 MOVM32mp 512, 16, $sp
22 MOVM32mp 1024, 20, $sp
23 MOVM32mp 2048, 24, $sp
24 MOVM32mp 8192, 28, $sp
94 MOVM32pm 0, $sp, 1
95 MOVM32pm 4, $sp, 2
[all …]
/llvm-project-15.0.7/compiler-rt/lib/orc/
H A Dmacho_tlv.arm64.S23 sub sp, sp, #REGISTER_SAVE_SPACE_SIZE
24 stp x29, x30, [sp, #16 * 1]
25 stp x27, x28, [sp, #16 * 2]
26 stp x25, x26, [sp, #16 * 3]
27 stp x23, x24, [sp, #16 * 4]
28 stp x21, x22, [sp, #16 * 5]
29 stp x19, x20, [sp, #16 * 6]
30 stp x17, x18, [sp, #16 * 7]
31 stp x15, x16, [sp, #16 * 8]
32 stp x13, x14, [sp, #16 * 9]
[all …]
H A Delfnix_tls.aarch64.S24 sub sp, sp, #REGISTER_SAVE_SPACE_SIZE
25 stp x29, x30, [sp, #16 * 1]
26 stp x27, x28, [sp, #16 * 2]
27 stp x25, x26, [sp, #16 * 3]
28 stp x23, x24, [sp, #16 * 4]
29 stp x21, x22, [sp, #16 * 5]
30 stp x19, x20, [sp, #16 * 6]
31 stp x17, x18, [sp, #16 * 7]
32 stp x15, x16, [sp, #16 * 8]
33 stp x13, x14, [sp, #16 * 9]
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/
H A Dstack-realignment.ll12 ; RV32I-NEXT: addi sp, sp, -32
20 ; RV32I-NEXT: andi sp, sp, -32
26 ; RV32I-NEXT: addi sp, sp, 32
31 ; RV64I-NEXT: addi sp, sp, -32
39 ; RV64I-NEXT: andi sp, sp, -32
45 ; RV64I-NEXT: addi sp, sp, 32
55 ; RV32I-NEXT: addi sp, sp, -16
62 ; RV32I-NEXT: addi sp, sp, 16
67 ; RV64I-NEXT: addi sp, sp, -16
74 ; RV64I-NEXT: addi sp, sp, 16
[all …]
H A Dstack-store-check.ll17 ; CHECK-NEXT: addi sp, sp, -688
40 ; CHECK-NEXT: sw s0, 596(sp)
41 ; CHECK-NEXT: sw s8, 592(sp)
42 ; CHECK-NEXT: sw s7, 588(sp)
46 ; CHECK-NEXT: sw s6, 584(sp)
48 ; CHECK-NEXT: lw s9, 616(sp)
49 ; CHECK-NEXT: lw s2, 620(sp)
50 ; CHECK-NEXT: lw s3, 624(sp)
51 ; CHECK-NEXT: lw s4, 628(sp)
52 ; CHECK-NEXT: sw s0, 548(sp)
[all …]
H A Ddouble-intrinsics.ll23 ; RV32I-NEXT: addi sp, sp, -16
27 ; RV32I-NEXT: addi sp, sp, 16
32 ; RV64I-NEXT: addi sp, sp, -16
36 ; RV64I-NEXT: addi sp, sp, 16
47 ; RV32IFD-NEXT: addi sp, sp, -16
51 ; RV32IFD-NEXT: addi sp, sp, 16
66 ; RV32I-NEXT: addi sp, sp, -16
70 ; RV32I-NEXT: addi sp, sp, 16
75 ; RV64I-NEXT: addi sp, sp, -16
80 ; RV64I-NEXT: addi sp, sp, 16
[all …]
H A Dfloat-intrinsics.ll34 ; RV32I-NEXT: addi sp, sp, -16
38 ; RV32I-NEXT: addi sp, sp, 16
43 ; RV64I-NEXT: addi sp, sp, -16
47 ; RV64I-NEXT: addi sp, sp, 16
58 ; RV32IF-NEXT: addi sp, sp, -16
62 ; RV32IF-NEXT: addi sp, sp, 16
72 ; RV64IF-NEXT: addi sp, sp, 16
77 ; RV32I-NEXT: addi sp, sp, -16
81 ; RV32I-NEXT: addi sp, sp, 16
86 ; RV64I-NEXT: addi sp, sp, -16
[all …]
H A Ddouble-intrinsics-strict.ll25 ; RV32I-NEXT: addi sp, sp, -16
29 ; RV32I-NEXT: addi sp, sp, 16
34 ; RV64I-NEXT: addi sp, sp, -16
38 ; RV64I-NEXT: addi sp, sp, 16
53 ; RV32IFD-NEXT: addi sp, sp, 16
68 ; RV32I-NEXT: addi sp, sp, -16
72 ; RV32I-NEXT: addi sp, sp, 16
77 ; RV64I-NEXT: addi sp, sp, -16
82 ; RV64I-NEXT: addi sp, sp, 16
115 ; RV32I-NEXT: addi sp, sp, 16
[all …]
H A Dfloat-intrinsics-strict.ll25 ; RV32I-NEXT: addi sp, sp, -16
29 ; RV32I-NEXT: addi sp, sp, 16
34 ; RV64I-NEXT: addi sp, sp, -16
38 ; RV64I-NEXT: addi sp, sp, 16
49 ; RV32IF-NEXT: addi sp, sp, -16
53 ; RV32IF-NEXT: addi sp, sp, 16
63 ; RV64IF-NEXT: addi sp, sp, 16
68 ; RV32I-NEXT: addi sp, sp, -16
72 ; RV32I-NEXT: addi sp, sp, 16
77 ; RV64I-NEXT: addi sp, sp, -16
[all …]
H A Dinterrupt-attr.ll56 ; CHECK-RV32-NEXT: addi sp, sp, -64
90 ; CHECK-RV32-NEXT: addi sp, sp, 64
95 ; CHECK-RV32-F-NEXT: addi sp, sp, -192
193 ; CHECK-RV32-F-NEXT: addi sp, sp, 192
198 ; CHECK-RV32-FD-NEXT: addi sp, sp, -320
296 ; CHECK-RV32-FD-NEXT: addi sp, sp, 320
301 ; CHECK-RV64-NEXT: addi sp, sp, -128
335 ; CHECK-RV64-NEXT: addi sp, sp, 128
554 ; CHECK-RV32-NEXT: addi sp, sp, -80
591 ; CHECK-RV32-NEXT: addi sp, sp, 80
[all …]
H A Datomic-load-store.ll14 ; RV32I-NEXT: addi sp, sp, -16
19 ; RV32I-NEXT: addi sp, sp, 16
29 ; RV64I-NEXT: addi sp, sp, -16
34 ; RV64I-NEXT: addi sp, sp, 16
48 ; RV32I-NEXT: addi sp, sp, -16
53 ; RV32I-NEXT: addi sp, sp, 16
63 ; RV64I-NEXT: addi sp, sp, -16
68 ; RV64I-NEXT: addi sp, sp, 16
82 ; RV32I-NEXT: addi sp, sp, -16
87 ; RV32I-NEXT: addi sp, sp, 16
[all …]
/llvm-project-15.0.7/compiler-rt/lib/xray/
H A Dxray_trampoline_mips64.S24 daddiu $sp, $sp, -144
31 sd $a4, 96($sp)
32 sd $a3, 88($sp)
33 sd $a2, 80($sp)
34 sd $a1, 72($sp)
35 sd $a0, 64($sp)
42 sdc1 $f13, 8($sp)
43 sdc1 $f12, 0($sp)
80 daddiu $sp, $sp, 144
94 daddiu $sp, $sp, -64
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/RISCV/rvv/
H A Dallocate-lmul-2-4-8.ll12 ; CHECK-NEXT: sub sp, sp, a0
15 ; CHECK-NEXT: add sp, sp, a0
26 ; CHECK-NEXT: sub sp, sp, a0
29 ; CHECK-NEXT: add sp, sp, a0
38 ; CHECK-NEXT: addi sp, sp, -48
44 ; CHECK-NEXT: sub sp, sp, a0
45 ; CHECK-NEXT: andi sp, sp, -32
49 ; CHECK-NEXT: addi sp, sp, 48
64 ; CHECK-NEXT: sub sp, sp, a0
80 ; CHECK-NEXT: sub sp, sp, a0
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/CSKY/
H A Datomic-cmpxchg.ll8 ; CSKY-NEXT: subi16 sp, sp, 4
10 ; CSKY-NEXT: subi16 sp, sp, 8
17 ; CSKY-NEXT: addi16 sp, sp, 8
19 ; CSKY-NEXT: addi16 sp, sp, 4
34 ; CSKY-NEXT: subi16 sp, sp, 4
36 ; CSKY-NEXT: subi16 sp, sp, 8
43 ; CSKY-NEXT: addi16 sp, sp, 8
45 ; CSKY-NEXT: addi16 sp, sp, 4
60 ; CSKY-NEXT: subi16 sp, sp, 4
62 ; CSKY-NEXT: subi16 sp, sp, 8
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-mca/AArch64/Exynos/
H A Dasimd-ld1.s6 ld1 {v0.s}[0], [sp]
7 ld1r {v0.2s}, [sp]
8 ld1 {v0.2s}, [sp]
13 ld1 {v0.d}[0], [sp]
14 ld1r {v0.2d}, [sp]
15 ld1 {v0.2d}, [sp]
21 ld1r {v0.2s}, [sp], #4
22 ld1 {v0.2s}, [sp], #8
28 ld1r {v0.2d}, [sp], #8
36 ld1 {v0.2s}, [sp], x0
[all …]
H A Dfloat-store.s6 stur d0, [sp, #2]
7 stur q0, [sp, #16]
9 str b0, [sp], #1
10 str q0, [sp], #16
12 str h0, [sp, #2]!
13 str q0, [sp, #16]!
15 str s0, [sp, #4]
16 str q0, [sp, #16]
21 str b0, [sp, x0]
22 str q0, [sp, x0]
[all …]
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_mips64.S11 daddiu $sp,$sp,-40
12 sd $s0,32($sp)
13 sd $ra,24($sp)
15 sd $gp,8($sp)
47 daddiu $sp,$sp,40
63 daddiu $sp,$sp,-40
99 daddiu $sp,$sp,40
115 daddiu $sp,$sp,-48
153 daddiu $sp,$sp,48
169 daddiu $sp,$sp,-48
[all …]
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_rtl_mips64.S11 daddiu $sp,$sp,-40
12 sd $s0,32($sp)
13 sd $ra,24($sp)
15 sd $gp,8($sp)
47 daddiu $sp,$sp,40
63 daddiu $sp,$sp,-40
99 daddiu $sp,$sp,40
115 daddiu $sp,$sp,-48
153 daddiu $sp,$sp,48
169 daddiu $sp,$sp,-48
[all …]
/llvm-project-15.0.7/llvm/test/tools/llvm-readobj/COFF/
H A Darm-unwind-packed.s525 sub sp, sp, #32
527 add sp, sp, #32
536 sub sp, sp, #16
538 add sp, sp, #16
547 sub sp, sp, #16
549 add sp, sp, #16
555 sub sp, sp, #16
557 add sp, sp, #16
564 sub sp, sp, #20
653 add sp, sp, #8
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dmachine-outliner-stack-fixup-thumb.mir27 $r0 = t2LDRi12 $sp, 0, 14, $noreg
28 $r0 = t2LDRi12 $sp, 4, 14, $noreg
57 t2STRHT $r0, $sp, 0, 14, $noreg
58 t2STRHT $r0, $sp, 4, 14, $noreg
62 t2STRHT $r0, $sp, 0, 14, $noreg
63 t2STRHT $r0, $sp, 4, 14, $noreg
191 ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
201 ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
211 ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
221 ;CHECK-NEXT: $lr, $sp = frame-destroy t2LDR_POST $sp, 8, 14 /* CC::al */, $noreg
[all …]
/llvm-project-15.0.7/compiler-rt/lib/builtins/riscv/
H A Dsave.S24 addi sp, sp, -64
41 addi sp, sp, -64
62 addi sp, sp, -64
73 add sp, sp, t1
88 addi sp, sp, -16
100 addi sp, sp, -112
111 addi sp, sp, -112
124 addi sp, sp, -112
137 addi sp, sp, -112
170 add sp, sp, t1
[all …]

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