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/llvm-project-15.0.7/llvm/test/MC/AMDGPU/
H A Dgfx7_asm_ds.s312 ds_write2_b32 v1, v2, v3 offset1:255
315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
345 ds_write2st64_b32 v1, v2, v3 offset1:255
1173 ds_read2_b32 v[5:6], v1 offset1:255
1203 ds_read2st64_b32 v[5:6], v1 offset1:255
1671 ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
2358 ds_read2_b64 v[5:8], v1 offset1:255
[all …]
H A Dgfx8_asm_ds.s312 ds_write2_b32 v1, v2, v3 offset1:255
315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
345 ds_write2st64_b32 v1, v2, v3 offset1:255
1116 ds_read2_b32 v[5:6], v1 offset1:255
1146 ds_read2st64_b32 v[5:6], v1 offset1:255
1623 ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
2310 ds_read2_b64 v[5:8], v1 offset1:255
[all …]
H A Dgfx9_asm_ds.s312 ds_write2_b32 v1, v2, v3 offset1:255
315 ds_write2_b32 v1, v2, v3 offset0:0 offset1:255
318 ds_write2_b32 v1, v2, v3 offset0:16 offset1:255
324 ds_write2_b32 v1, v2, v3 offset0:127 offset1:0
327 ds_write2_b32 v1, v2, v3 offset0:127 offset1:1
345 ds_write2st64_b32 v1, v2, v3 offset1:255
1134 ds_read2_b32 v[5:6], v1 offset1:255
1164 ds_read2st64_b32 v[5:6], v1 offset1:255
1641 ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
2496 ds_read2_b64 v[5:8], v1 offset1:255
[all …]
H A Dgfx10_asm_ds.s1391 ds_write2_b32 v0, v1, v2 offset0:0 offset1:123
1406 ds_write2_b32 v0, v1, v2 offset0:123 offset1:0
4643 ds_read2_b32 v[5:6], v1 offset1:255
4646 ds_read2_b32 v[5:6], v1 offset0:0 offset1:255
4655 ds_read2_b32 v[5:6], v1 offset0:127 offset1:0
4658 ds_read2_b32 v[5:6], v1 offset0:127 offset1:1
4673 ds_read2st64_b32 v[5:6], v1 offset1:255
5141 ds_write2_b64 v1, v[2:3], v[3:4] offset1:255
5948 ds_read2_b64 v[5:8], v1 offset1:255
5951 ds_read2_b64 v[5:8], v1 offset0:0 offset1:255
[all …]
H A Dgfx11_ds.s21 ds_wrxchg2_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
24 ds_wrxchg2st64_rtn_b32 v[254:255], v1, v2, v3 offset0:127 offset1:255
30 ds_read2_b32 v[254:255], v1 offset0:127 offset1:255
33 ds_read2st64_b32 v[254:255], v1 offset0:127 offset1:255
51 ds_write2_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
54 ds_write2st64_b64 v1, v[254:255], v[3:4] offset0:127 offset1:255
60 ds_wrxchg2_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
63 ds_wrxchg2st64_rtn_b64 v[252:255], v1, v[2:3], v[3:4] offset0:127 offset1:255
69 ds_read2_b64 v[252:255], v1 offset0:127 offset1:255
72 ds_read2st64_b64 v[252:255], v1 offset0:127 offset1:255
H A Dds.s42 ds_write2_b32 v2, v4, v6 offset0:4 offset1:8
46 ds_write2_b32 v2, v4, v6 offset1:8
54 ds_read2_b32 v[8:9], v2 offset0:4 offset1:8
58 ds_read2_b32 v[8:9], v2 offset1:8
250 ds_wrxchg2_rtn_b32 v[0:1], v0, v0, v0 offset0:127 offset1:255
258 ds_wrxchg2st64_rtn_b32 v[0:1], v0, v255, v0 offset0:127 offset1:255
459 ds_wrxchg2_rtn_b64 v[0:3], v0, v[1:2], v[0:1] offset0:127 offset1:255
467 ds_wrxchg2st64_rtn_b64 v[0:3], v255, v[0:1], v[0:1] offset0:127 offset1:255
H A Dds-err.s18 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
30 ds_write2_b32 v2, v4, v6 offset1:1000000000
34 ds_write2_b32 v2, v4, v6 offset1:0x100
H A Dgfx90a_ldst_acc.s7222 ds_write2_b32 v1, a2, a3 offset1:255
7226 ds_write2_b32 v1, a2, a3 offset1:255
7266 ds_write2st64_b32 v1, a2, a3 offset1:255
8290 ds_read2_b32 a[6:7], v1 offset1:255
8294 ds_read2_b32 a[6:7], v1 offset1:255
8330 ds_read2st64_b32 a[6:7], v1 offset1:255
8334 ds_read2st64_b32 a[6:7], v1 offset1:255
10106 ds_read2_b64 a[6:9], v1 offset1:255
10110 ds_read2_b64 a[6:9], v1 offset1:255
10146 ds_read2st64_b64 a[6:9], v1 offset1:255
[all …]
H A Dgfx90a_err.s165 ds_write2_b64 v1, a[4:5], v[2:3] offset1:255
168 ds_write2_b64 v1, v[4:5], a[2:3] offset1:255
171 ds_write2_b64 v1, a[4:5], v[2:3] offset1:255 gds
174 ds_write2_b64 v1, v[4:5], a[2:3] offset1:255 gds
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds-combine-large-stride.ll16 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
17 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset0:72 offset1:172
18 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:144 offset1:244
19 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B3]] offset0:88 offset1:188
62 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[B2]] offset0:8 offset1:28
105 ; GCN-DAG: ds_read2_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:100
141 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:32
181 ; GCN-DAG: ds_read2st64_b32 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:32
215 ; GCN-DAG: ds_read2_b64 v[{{[0-9]+:[0-9]+}}], [[BASE]] offset1:50
255 ; GCN-DAG: ds_read2st64_b64 v[{{[0-9]+:[0-9]+}}], [[B1]] offset1:16
[all …]
H A Dreduce-store-width-alignment.ll5 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
14 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
15 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
24 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
33 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:2 offset1:3
34 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
46 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset1:1{{$}}
H A Dload-local-i16.ll82 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
100 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
315 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
332 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
357 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
385 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
423 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
424 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3
425 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5
457 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
[all …]
H A Dfence-lds-read2-write2.ll18 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:66
19 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
20 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:74
21 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:206
28 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset1:66
29 ; GCN-NEXT: ds_write2_b64 v2, v[0:1], v[0:1] offset0:132 offset1:198
30 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:8 offset1:74
31 ; GCN-NEXT: ds_write2_b64 v3, v[0:1], v[0:1] offset0:140 offset1:206
H A Dds_read2_superreg.ll11 ; CI: ds_read2_b32 [[RESULT:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
39 ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
65 ; CI-DAG: ds_read2_b32 v[[[REG_X:[0-9]+]]:[[REG_Y:[0-9]+]]], v{{[0-9]+}} offset1:1{{$}}
88 ; CI: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
101 ; CI-DAG: ds_read2_b64 [[REG_ZW:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
115 ; CI-DAG: ds_read2_b64 [[VEC_HI:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
116 ; CI-DAG: ds_read2_b64 [[VEC_LO:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
131 ; CI-DAG: ds_read2_b64 [[VEC0_3:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset1:1{{$}}
132 ; CI-DAG: ds_read2_b64 [[VEC4_7:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:2 offset1:3{{$}}
133 ; CI-DAG: ds_read2_b64 [[VEC8_11:v\[[0-9]+:[0-9]+\]]], v{{[0-9]+}} offset0:4 offset1:5{{$}}
[all …]
H A Dds_write2.ll21 ; CI-NEXT: ds_write2_b32 v0, v1, v1 offset1:8
31 ; GFX9-NEXT: ds_write2_b32 v0, v1, v1 offset1:8
58 ; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:8
70 ; GFX9-NEXT: ds_write2_b32 v0, v1, v2 offset1:8
197 ; CI-NEXT: ds_write2_b32 v0, v3, v2 offset1:8
212 ; GFX9-NEXT: ds_write2_b32 v0, v1, v3 offset1:8
242 ; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:8
281 ; CI-NEXT: ds_write2_b32 v0, v1, v4 offset1:8
410 ; CI-NEXT: ds_write2_b32 v0, v2, v1 offset1:8
615 ; CI-NEXT: ds_write2_b32 v0, v1, v2 offset1:1
[all …]
H A Dload-local-i32.ll56 ; GCN: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
69 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
70 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
82 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:6 offset1:7{{$}}
83 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:4 offset1:5{{$}}
84 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:2 offset1:3{{$}}
85 ; GCN-DAG: ds_read2_b64 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset1:1{{$}}
86 …-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:6 offset1:7
87 …-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:4 offset1:5
88 …-DAG: ds_write2_b64 v{{[0-9]+}}, v{{\[[0-9]+:[0-9]+\]}}, v{{\[[0-9]+:[0-9]+\]}} offset0:2 offset1:3
[all …]
H A Dds-combine-with-dependence.ll9 ; GCN-DAG: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
10 ; GCN-DAG: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:8
42 ; GCN: ds_read2_b32 v{{\[[0-9]+:[0-9]+\]}}, v{{[0-9]+}} offset0:7 offset1:27
43 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
75 ; GCN: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
109 ; GCN-NEXT: ds_write2_b32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}} offset0:26 offset1:27
H A Dds_read2_offset_order.ll6 ; offset0 is larger than offset1
11 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:11 offset1:12
12 ; SI-DAG: ds_read2_b32 v[{{[0-9]+}}:{{[0-9]+}}], v{{[0-9]+}} offset0:6 offset1:248
H A Dds_read2.ll17 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
30 ; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:8
53 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:255
66 ; GFX9-NEXT: ds_read2_b32 v[0:1], v2 offset1:255
127 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
143 ; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8
183 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
201 ; GFX9-NEXT: ds_read2_b32 v[0:1], v4 offset1:8
412 ; CI-NEXT: ds_read2_b32 v[1:2], v0 offset1:8
790 ; CI-NEXT: ds_read2_b64 v[0:3], v4 offset1:8
[all …]
/llvm-project-15.0.7/compiler-rt/lib/asan/
H A Dasan_interceptors_memintrinsics.h131 static inline bool RangesOverlap(const char *offset1, uptr length1, in DECLARE_REAL()
133 return !((offset1 + length1 <= offset2) || (offset2 + length2 <= offset1)); in DECLARE_REAL()
137 const char *offset1 = (const char *)_offset1; \ in DECLARE_REAL()
139 if (RangesOverlap(offset1, length1, offset2, length2)) { \ in DECLARE_REAL()
146 ReportStringFunctionMemoryRangesOverlap(name, offset1, length1, \ in DECLARE_REAL()
/llvm-project-15.0.7/llvm/test/tools/dsymutil/X86/
H A Dop-convert-offset.test9 # $ cat op-convert-offset1.c
17 # $ xcrun clang -g -O2 -c -target x86_64-apple-unknown-macho op-convert-offset1.c -emit-llvm
19 # $ llvm-link op-convert-offset1.bc op-convert-offset0.bc -o op-convert-offset.ll -S
/llvm-project-15.0.7/llvm/test/CodeGen/Mips/
H A Deh-return32.ll19 ; CHECK: sw $5, [[offset1:[0-9]+]]($sp)
37 ; CHECK: lw $5, [[offset1]]($sp)
61 ; CHECK: sw $5, [[offset1:[0-9]+]]($sp)
77 ; CHECK: lw $5, [[offset1]]($sp)
H A Deh-return64.ll20 ; CHECK: sd $5, [[offset1:[0-9]+]]($sp)
38 ; CHECK: ld $5, [[offset1]]($sp)
64 ; CHECK: sd $5, [[offset1:[0-9]+]]($sp)
80 ; CHECK: ld $5, [[offset1]]($sp)
/llvm-project-15.0.7/polly/test/IstAstInfo/
H A Dsimple-run-time-condition.ll51 %offset1 = add nsw i64 %j, %q
52 %subscript1 = add i64 %offset1, %subscript0
75 %offset1.1 = add nsw i64 %j.1, %q
76 %subscript1.1 = add i64 %offset1.1, %subscript0.1
/llvm-project-15.0.7/llvm/test/Analysis/ValueTracking/
H A Dmemory-dereferenceable.ll97 ; GLOBAL: %gep.align1.offset1{{.*}}(unaligned)
98 ; GLOBAL: %gep.align16.offset1{{.*}}(unaligned)
101 ; POINT-NOT: %gep.align1.offset1{{.*}}(unaligned)
102 ; POINT-NOT: %gep.align16.offset1{{.*}}(unaligned)
105 %gep.align1.offset1 = getelementptr inbounds i8, i8 addrspace(1)* %dparam.align1, i32 1
106 %gep.align16.offset1 = getelementptr inbounds i8, i8 addrspace(1)* %dparam.align16, i32 1
109 %load19 = load i8, i8 addrspace(1)* %gep.align1.offset1, align 16
110 %load20 = load i8, i8 addrspace(1)* %gep.align16.offset1, align 16

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