| /llvm-project-15.0.7/llvm/test/MC/X86/ |
| H A D | I286-32.s | 85 lsll 3809469200(%edx,%eax,4), %eax label 89 lsll 485498096, %eax label 93 lsll 485498096(%edx,%eax,4), %eax label 97 lsll 485498096(%edx), %eax label 101 lsll 64(%edx,%eax), %eax label 105 lsll %eax, %eax label 109 lsll (%edx), %eax label
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| H A D | I286-64.s | 149 lsll 485498096, %r13d label 153 lsll 64(%rdx), %r13d label 157 lsll 64(%rdx,%rax,4), %r13d label 161 lsll -64(%rdx,%rax,4), %r13d label 165 lsll 64(%rdx,%rax), %r13d label 169 lsll %r13d, %r13d label 173 lsll (%rdx), %r13d label
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/mve-intrinsics/ |
| H A D | longshift-const.ll | 5 declare {i32, i32} @llvm.arm.mve.lsll(i32, i32, i32) 126 ; CHECK-NEXT: lsll r0, r1, #2 145 ; CHECK-NEXT: lsll r0, r1, #32 212 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 0) 225 ; CHECK-NEXT: lsll r0, r1, #23 244 ; CHECK-NEXT: lsll r0, r1, #32 264 ; CHECK-NEXT: lsll r0, r1, r2 284 ; CHECK-NEXT: lsll r0, r1, r2 304 ; CHECK-NEXT: lsll r0, r1, r2 362 ; CHECK-NEXT: lsll r0, r1, r2 [all …]
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| H A D | longshift-demand.ll | 30 ; CHECK-NEXT: lsll r0, r1, #3 50 ; CHECK-NEXT: lsll r0, r1, #3 111 ; CHECK-NEXT: lsll r0, r1, #31 131 ; CHECK-NEXT: lsll r0, r1, #31 192 ; CHECK-NEXT: lsll r0, r1, #32 212 ; CHECK-NEXT: lsll r0, r1, #32 275 ; CHECK-NEXT: lsll r0, r1, r2 317 ; CHECK-NEXT: lsll r0, r1, r2 365 ; CHECK-NEXT: lsll r0, r1, #3 387 ; CHECK-NEXT: lsll r0, r1, #3 [all …]
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| H A D | scalar-shifts.ll | 28 ; CHECK-NEXT: lsll r0, r1, r2 34 %3 = call { i32, i32 } @llvm.arm.mve.lsll(i32 %2, i32 %1, i32 %shift) 44 declare { i32, i32 } @llvm.arm.mve.lsll(i32, i32, i32)
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/ |
| H A D | mve-shifts.ll | 41 ; CHECK-NEXT: lsll r2, r1, r0 44 ; CHECK-NEXT: lsll r0, r5, r3 96 ; CHECK-NEXT: lsll r0, r5, r2 99 ; CHECK-NEXT: lsll r2, r3, r1 197 ; CHECK-NEXT: lsll r0, r1, #4 198 ; CHECK-NEXT: lsll r2, r3, #4 341 ; CHECK-NEXT: lsll r12, r1, r0 342 ; CHECK-NEXT: lsll r2, r3, r0 401 ; CHECK-NEXT: lsll r2, r1, r3 402 ; CHECK-NEXT: lsll r0, r5, r3
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| H A D | mve-vcreate.ll | 237 ; CHECK-NEXT: lsll r2, r7, #16 242 ; CHECK-NEXT: lsll r4, r5, #16 314 ; CHECK-NEXT: lsll r4, r11, #16 316 ; CHECK-NEXT: lsll r6, r7, #24 322 ; CHECK-NEXT: lsll r6, r3, #8 326 ; CHECK-NEXT: lsll r4, r5, #16 331 ; CHECK-NEXT: lsll r6, r1, #24 334 ; CHECK-NEXT: lsll r4, r9, #8
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| H A D | mve-laneinterleaving.ll | 375 ; CHECK-NEXT: lsll r0, r5, r6 377 ; CHECK-NEXT: lsll r0, r5, r2 384 ; CHECK-NEXT: lsll r4, r7, r2 386 ; CHECK-NEXT: lsll r4, r7, r1 409 ; CHECK-NEXT: lsll r0, r9, r3 415 ; CHECK-NEXT: lsll r0, r9, r1 422 ; CHECK-NEXT: lsll r4, r5, r3 423 ; CHECK-NEXT: lsll r4, r5, r2
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| H A D | shift_parts.ll | 8 ; CHECK-MVE-NEXT: lsll r0, r1, r2 32 ; CHECK-MVE-NEXT: lsll r0, r1, #3 83 ; CHECK-MVE-NEXT: lsll r0, r1, r2 203 ; CHECK-MVE-NEXT: lsll r2, r1, #8
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| /llvm-project-15.0.7/llvm/test/MC/ARM/ |
| H A D | mve-scalar-shift.s | 94 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21] 96 lsll lr, r1, #11 label 98 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41] 100 lsll lr, r1, r4 label
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| /llvm-project-15.0.7/llvm/test/CodeGen/M68k/ShiftRotate/ |
| H A D | lsl.ll | 32 define i32 @lsll(i32 %a, i32 %b) nounwind { 33 ; CHECK-LABEL: lsll:
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| /llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/ |
| H A D | mve-scalar-shift.txt | 18 # CHECK: lsll lr, r1, #11 @ encoding: [0x5e,0xea,0xcf,0x21] 22 # CHECK: lsll lr, r1, r4 @ encoding: [0x5e,0xea,0x0d,0x41]
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| /llvm-project-15.0.7/clang/test/CodeGen/arm-mve-intrinsics/ |
| H A D | scalar-shifts.c | 43 return lsll(value, shift); in test_lsll()
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| /llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/LowOverheadLoops/ |
| H A D | while-loops.ll | 207 ; CHECK-NEXT: lsll r0, r1, #30 211 ; CHECK-NEXT: lsll r0, r11, r4 215 ; CHECK-NEXT: lsll r0, r11, r1
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| /llvm-project-15.0.7/clang/include/clang/Basic/ |
| H A D | arm_mve.td | 1270 def lsll: LongScalarShift<u64, (args s32:$sh), (IRInt<"lsll"> $lo, $hi, $sh)>;
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMInstrMVE.td | 574 def MVE_LSLLr : MVE_ScalarShiftDRegReg<"lsll", 0b0, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi, 577 def MVE_LSLLi : MVE_ScalarShiftDRegImm<"lsll", 0b00, ?, [(set tGPREven:$RdaLo, tGPROdd:$RdaHi,
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