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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dpostlegalizercombiner-and.mir41 ; CHECK-NEXT: %smin:_(s32) = G_SMIN %load0, %load1
47 %smin:_(s32) = G_SMIN %load0, %load1
68 ; CHECK-NEXT: %smax:_(s32) = G_SMAX %load0, %load1
74 %smax:_(s32) = G_SMAX %load0, %load1
95 ; CHECK-NEXT: %umin:_(s32) = G_UMIN %load0, %load1
101 %umin:_(s32) = G_UMIN %load0, %load1
122 ; CHECK-NEXT: %umax:_(s32) = G_UMAX %load0, %load1
128 %umax:_(s32) = G_UMAX %load0, %load1
150 ; CHECK-NEXT: %smin:_(s32) = G_SMIN %load0, %load1
158 %smin:_(s32) = G_SMIN %load0, %load1
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/LoadStoreVectorizer/X86/
H A Dcompare-scev-by-complexity.ll23 ; CHECK: [[PTR:%[0-9]+]] = bitcast float* %preheader.load0.address to <2 x float>*
41 …%preheader.load0.address = getelementptr inbounds float, float* @other_value, i64 %preheader.addre…
42 %preheader.load0. = load float, float* %preheader.load0.address, align 4, !tbaa !1
50 …%loop.header.load0.address = getelementptr inbounds float, float* @other_value, i64 %preheader.hea…
51 %loop.header.load0. = load float, float* %loop.header.load0.address, align 4, !tbaa !1
59 store float %preheader.load0., float* @a, align 4, !tbaa !1
61 store float %loop.header.load0., float* @c, align 4, !tbaa !1
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dds-combine-with-dependence.ll18 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
19 %v0 = extractelement <3 x float> %load0, i32 2
50 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
51 %v0 = extractelement <3 x float> %load0, i32 2
84 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
85 %v0 = extractelement <3 x float> %load0, i32 2
117 %load0 = load <3 x float>, <3 x float> addrspace(3)* %vaddr0, align 4
118 %v0 = extractelement <3 x float> %load0, i32 2
H A Dvselect.ll22 %load0 = load <2 x i32>, <2 x i32> addrspace(1)* %in0
24 %cmp = icmp sgt <2 x i32> %load0, %load1
25 %result = select <2 x i1> %cmp, <2 x i32> %val, <2 x i32> %load0
69 %load0 = load <4 x i32>, <4 x i32> addrspace(1)* %in0
71 %cmp = icmp sgt <4 x i32> %load0, %load1
72 %result = select <4 x i1> %cmp, <4 x i32> %val, <4 x i32> %load0
H A Dcontrol-flow-fastregalloc.ll69 %load0 = load volatile i32, i32 addrspace(3)* undef
75 %val = add i32 %load0, %load1
139 %load0 = load volatile i32, i32 addrspace(3)* null
145 %val = phi i32 [ %val.sub, %loop ], [ %load0, %entry ]
249 %load0 = load volatile i32, i32 addrspace(3)* null
255 %val0 = add i32 %load0, %load1
260 %val1 = sub i32 %load0, %load2
H A Dschedule-global-loads.ll14 %load0 = load i32, i32 addrspace(1)* %ptr, align 4
17 store i32 %load0, i32 addrspace(1)* %out0, align 4
H A Dglobal_smrd.ll111 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
112 %load1 = load i32, i32 addrspace(1)* %load0, align 4
130 %load0 = load i32 addrspace(1)*, i32 addrspace(1)* addrspace(1)* @A, align 4
131 %load1 = load i32, i32 addrspace(1)* %load0, align 4
H A Dtrunc-combine.ll46 %load0 = load i32, i32 addrspace(1)* undef
48 %insert.0 = insertelement <2 x i32> undef, i32 %load0, i32 0
75 %load0 = load float, float addrspace(1)* undef
77 %insert.0 = insertelement <2 x float> undef, float %load0, i32 0
H A Dlocal-stack-alloc-block-sp-reference.ll100 %load0 = load volatile i64, i64 addrspace(5)* %gep.large.offset
102 %add0 = add i64 %load0, %load1
196 %load0 = load volatile i64, i64 addrspace(5)* %gep.large.offset
198 %add0 = add i64 %load0, %load1
327 %load0 = load volatile <3 x i64>, <3 x i64> addrspace(5)* %gep.large.offset
329 %add0 = add <3 x i64> %load0, %load1
H A Dload-hi16.ll887 %load0 = load volatile i16, i16 addrspace(3)* %in
889 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
923 %load0 = load i16, i16 addrspace(3)* %in
924 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
960 %load0 = load volatile i16, i16 addrspace(1)* %in
962 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
979 %load0 = load volatile i16, i16* %in
981 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
998 %load0 = load volatile i16, i16 addrspace(4)* %in
1000 %build0 = insertelement <2 x i16> undef, i16 %load0, i32 0
[all …]
H A Doverlapping-tuple-copy-implicit-op-failure.ll96 %load0 = load <4 x i64>, <4 x i64> addrspace(1)* null, align 32
98 %add = add <4 x i64> %load0, %load1
H A Dllvm.amdgcn.s.buffer.load.ll181 %load0 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 4, i32 0)
183 %x = bitcast i32 %load0 to float
196 %load0 = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> %desc, i32 8, i32 0)
200 %x = bitcast i32 %load0 to float
H A Dllvm.amdgcn.implicitarg.ptr.ll256 %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
272 %load0 = load volatile i32, i32 addrspace(4)* %cast.kernarg.segment.ptr
/llvm-project-15.0.7/llvm/test/Linker/
H A Dwrong-addrspace-gv-declaration.ll11 ; CHECK: %load0 = load volatile i32, ptr addrspacecast (ptr addrspace(1) @is_really_as1_gv to ptr),…
14 %load0 = load volatile i32, ptr @is_really_as1_gv, align 4
/llvm-project-15.0.7/llvm/test/Transforms/TypePromotion/ARM/
H A Dsigned-icmps.ll18 %load0 = load i8, i8* %x, align 1
20 %add = add i8 %load0, %z
42 %load0 = load i16, i16* %x, align 1
43 %add = add i16 %load0, %z
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/AArch64/
H A Dinvalid_type.ll17 %load0 = tail call <16 x i8> @vector.load(<16 x i8> *undef, i32 1)
19 %add = add <16 x i8> %load1, %load0
H A Dext-trunc.ll38 %load0 = load i64, i64* %gep0
51 call void @foo(i64 %load0, i64 %load1, i64 %load2, i64 %load3)
90 %load0 = load i64, i64* %gep0
106 call void @foo(i64 %load0, i64 %load1, i64 %load2, i64 %load3)
H A Dscalable-vector.ll17 …%load0 = tail call <vscale x 16 x i8> @llvm.masked.load.nxv16i8.p0nxv16i8(<vscale x 16 x i8> *unde…
19 %add = add <vscale x 16 x i8> %load1, %load0
/llvm-project-15.0.7/llvm/test/Transforms/InferAddressSpaces/AMDGPU/
H A Dinsert-pos-assert.ll27 …%load0 = load i32*, i32* addrspace(4)* getelementptr inbounds (%struct.s1, %struct.s1 addrspace(4)…
30 %gep = getelementptr inbounds i32, i32* %load0, i64 %sext
64 %load0 = load double*, double** %itp0, align 8
H A Dptrmask.ll142 %load0 = load i8, i8* %cast
145 %add = add i8 %load0, %load1
160 %load0 = load i8, i8* %cast
163 %add = add i8 %load0, %load1
177 %load0 = load i8, i8* %cast
180 %add = add i8 %load0, %load1
/llvm-project-15.0.7/llvm/test/Transforms/NewGVN/
H A Daddrspacecast.ll99 %load0 = load i32*, i32** %arg.ptr
100 %z1 = addrspacecast i32* %load0 to i32 addrspace(1)*
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonShuffler.cpp500 ++Summary.load0; in GetPacketSummary()
539 ++Summary.load0; in GetPacketSummary()
578 ((Summary.load0 > 1 || Summary.store0 > 1 || !ValidHVXMem) || in ValidPacketMemoryOps()
H A DHexagonShuffler.h141 unsigned load0; member
/llvm-project-15.0.7/llvm/test/Instrumentation/DataFlowSanitizer/
H A Dload.ll12 define {} @load0({}* %p) {
13 ; CHECK-LABEL: @load0.dfsan
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Df16-convert.ll3 define float @load0(i16* nocapture readonly %a) nounwind {
4 ; CHECK-LABEL: load0:

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