Searched refs:gorcw (Results 1 – 8 of 8) sorted by relevance
| /llvm-project-15.0.7/llvm/test/MC/RISCV/ |
| H A D | rv64zbp-valid.s | 55 # CHECK-ASM-AND-OBJ: gorcw t0, t1, t2
57 gorcw t0, t1, t2 label
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| H A D | rv64zbp-invalid.s | 4 gorcw t0, t1 # CHECK: :[[@LINE]]:1: error: too few operands for instruction label
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| H A D | rv32zbp-invalid.s | 43 gorcw t0, t1, t2 # CHECK: :[[@LINE]]:1: error: instruction requires the following: RV64I Base Instr… label
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| H A D | rv64zbp-aliases-valid.s | 340 gorcw x5, x6, 13 label
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| /llvm-project-15.0.7/clang/test/CodeGen/RISCV/rvb-intrinsics/ |
| H A D | riscv64-zbp.c | 112 int gorcw(int rs1, int rs2) in gorcw() function
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| /llvm-project-15.0.7/llvm/lib/Target/RISCV/ |
| H A D | RISCVScheduleB.td | 52 def WriteORC32 : SchedWrite; // gorcw
132 def ReadORC32 : SchedRead; // gorcw
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| H A D | RISCVInstrInfoZb.td | 430 def GORCW : ALUW_rr<0b0010100, 0b101, "gorcw">,
790 def : InstAlias<"gorcw $rd, $rs1, $shamt",
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| /llvm-project-15.0.7/llvm/test/CodeGen/RISCV/ |
| H A D | rv64zbp-intrinsic.ll | 51 ; RV64ZBP-NEXT: gorcw a0, a0, a1
61 ; RV64ZBP-NEXT: gorcw a0, a0, a2
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