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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmicromips-fpu-instructions.s377 c.f.s $f6, $f7
378 c.un.s $f6, $f7
379 c.eq.s $f6, $f7
380 c.olt.s $f6, $f7
381 c.ult.s $f6, $f7
382 c.ole.s $f6, $f7
383 c.ule.s $f6, $f7
384 c.sf.s $f6, $f7
385 c.ngle.s $f6, $f7
386 c.seq.s $f6, $f7
[all …]
H A Dmips-fpu-instructions.s31 abs.s $f6,$f7
35 floor.w.s $f6,$f7
37 ceil.w.s $f6,$f7
41 neg.s $f6,$f7
43 round.w.s $f6,$f7
133 cvt.d.s $f6,$f7
136 cvt.s.w $f6,$f7
138 cvt.w.s $f6,$f7
186 mov.d $f6,$f8
187 mov.s $f6,$f7
[all …]
H A Dmips_directives.s54 .set f6,$f6 define
56 # CHECK: abs.s $f6, $f7 # encoding: [0x46,0x00,0x39,0x85]
59 abs.s f6,FPU_MASK
65 # CHECK: lwxc1 $f6, $2($5) # encoding: [0x4c,0xa2,0x01,0x80]
69 lwxc1 $f6, $2($5)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32/
H A Dvalid-mips32-el.txt3 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
6 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
26 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
28 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
30 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
32 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
34 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
36 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
40 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
48 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips32.txt176 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
177 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
178 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
179 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
197 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
198 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
199 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
204 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
208 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
210 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/micromips32r3/
H A Dvalid.txt258 0x54 0x86 0x28 0x3b # CHECK: mtc1 $4, $f6
259 0x54 0x86 0x20 0x3b # CHECK: mfc1 $4, $f6
260 0x54 0x86 0x38 0x3b # CHECK: mthc1 $4, $f6
261 0x54 0x86 0x30 0x3b # CHECK: mfhc1 $4, $f6
262 0x54 0xe6 0x00 0x3c # CHECK: c.f.s $f6, $f7
263 0x54 0xe6 0x00 0x7c # CHECK: c.un.s $f6, $f7
264 0x54 0xe6 0x00 0xbc # CHECK: c.eq.s $f6, $f7
265 0x54 0xe6 0x01 0x3c # CHECK: c.olt.s $f6, $f7
266 0x54 0xe6 0x01 0x7c # CHECK: c.ult.s $f6, $f7
267 0x54 0xe6 0x01 0xbc # CHECK: c.ole.s $f6, $f7
[all …]
H A Dvalid-el.txt114 0xe6 0x54 0x78 0x20 # CHECK: movz.s $f4, $f6, $7
115 0xe6 0x54 0x78 0x21 # CHECK: movz.d $f4, $f6, $7
116 0xe6 0x54 0x38 0x20 # CHECK: movn.s $f4, $f6, $7
117 0xe6 0x54 0x38 0x21 # CHECK: movn.d $f4, $f6, $7
216 0x46,0x56,0x3b,0x52 # CHECK: recip.d $f18, $f6
246 0xc8 0x54 0x3b 0x1b # CHECK: ceil.w.s $f6, $f8
247 0xc8 0x54 0x3b 0x5b # CHECK: ceil.w.d $f6, $f8
256 0x86 0x54 0x3b 0x28 # CHECK: mtc1 $4, $f6
257 0x86 0x54 0x3b 0x20 # CHECK: mfc1 $4, $f6
258 0x86 0x54 0x3b 0x38 # CHECK: mthc1 $4, $f6
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r5/
H A Dvalid-mips32r5-el.txt4 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
7 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
26 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
28 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
30 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
32 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
34 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
36 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
40 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
48 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips32r5.txt187 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
188 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
189 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
190 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
209 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
210 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
211 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
216 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
220 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
222 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r3/
H A Dvalid-mips32r3-el.txt4 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
7 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
26 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
28 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
30 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
32 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
34 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
36 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
40 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
48 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips32r3.txt187 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
188 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
189 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
190 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
209 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
210 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
211 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
216 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
220 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
222 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips32r2/
H A Dvalid-mips32r2-el.txt7 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
10 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
29 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
31 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
33 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
35 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
37 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
39 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
43 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
51 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips32r2.txt190 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
191 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
192 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
193 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
212 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
213 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
214 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
219 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
223 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
225 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r3/
H A Dvalid-mips64r3-el.txt4 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
8 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
27 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
29 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
31 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
33 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
35 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
37 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
41 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
49 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r5/
H A Dvalid-mips64r5-el.txt4 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
8 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
27 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
29 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
31 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
33 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
35 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
37 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
41 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
49 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64/
H A Dvalid-mips64-el.txt3 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
6 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
24 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
26 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
28 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
30 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
32 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
34 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
38 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
46 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips64.txt228 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
229 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
230 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
231 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
252 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
253 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
254 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
259 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
263 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
265 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/MC/Disassembler/Mips/mips64r2/
H A Dvalid-mips64r2-el.txt7 0x85 0x39 0x00 0x46 # CHECK: abs.s $f6, $f7
11 0x40 0x32 0x07 0x46 # CHECK: add.s $f9, $f6, $f7
30 0x32 0x30 0x07 0x46 # CHECK: c.eq.s $f6, $f7
32 0x30 0x30 0x07 0x46 # CHECK: c.f.s $f6, $f7
34 0x3e 0x30 0x07 0x46 # CHECK: c.le.s $f6, $f7
36 0x3c 0x30 0x07 0x46 # CHECK: c.lt.s $f6, $f7
38 0x3d 0x30 0x07 0x46 # CHECK: c.nge.s $f6, $f7
40 0x3b 0x30 0x07 0x46 # CHECK: c.ngl.s $f6, $f7
44 0x3f 0x30 0x07 0x46 # CHECK: c.ngt.s $f6, $f7
52 0x38 0x30 0x07 0x46 # CHECK: c.sf.s $f6, $f7
[all …]
H A Dvalid-mips64r2.txt249 0x46 0x00 0x39 0x84 # CHECK: sqrt.s $f6, $f7
250 0x46 0x00 0x39 0x85 # CHECK: abs.s $f6, $f7
251 0x46 0x00 0x39 0x86 # CHECK: mov.s $f6, $f7
252 0x46 0x00 0x39 0x87 # CHECK: neg.s $f6, $f7
274 0x46 0x07 0x30 0x30 # CHECK: c.f.s $f6, $f7
275 0x46 0x07 0x30 0x31 # CHECK: c.un.s $f6, $f7
276 0x46 0x07 0x30 0x32 # CHECK: c.eq.s $f6, $f7
281 0x46 0x07 0x30 0x38 # CHECK: c.sf.s $f6, $f7
285 0x46 0x07 0x30 0x3c # CHECK: c.lt.s $f6, $f7
287 0x46 0x07 0x30 0x3e # CHECK: c.le.s $f6, $f7
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dcortex-a57-misched-vfma.ll6 …ne arm_aapcs_vfpcc float @Test1(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
35 ; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
38 %mul3 = fmul float %f5, %f6
45 … float> %f1, <2 x float> %f2, <2 x float> %f3, <2 x float> %f4, <2 x float> %f5, <2 x float> %f6) {
74 ; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLAS, VMLAS
77 %mul3 = fmul <2 x float> %f5, %f6
83 …ne arm_aapcs_vfpcc float @Test3(float %f1, float %f2, float %f3, float %f4, float %f5, float %f6) {
112 ; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
115 %mul3 = fmul float %f5, %f6
151 ; f1 * f2 + f3 * f4 + f5 * f6 ==> VMULS, VMLSS, VMLSS
[all …]
/llvm-project-15.0.7/clang/test/SemaCXX/
H A Dwarn-cast-function-type.cpp10 typedef int (f6)(long, int); typedef
19 f6 *f;
37 …f = (f6 *)x; /* expected-warning {{cast from 'int (*)(long)' to 'f6 *' (aka 'int (*)(long, int)') … in foo()
46 …f = (f6 *)y; /* expected-warning {{cast from 'int (^)(long)' to 'f6 *' (aka 'int (*)(long, int)') … in foo()
/llvm-project-15.0.7/clang/test/CodeGen/
H A Dinline2.c31 inline int f6(void);
32 extern inline int f6(void) { return 0; } in f6() function
65 return f0() + f1() + f2() + f3() + f4() + f5() + f6() + f7() + f8() + f9() in test_all()
/llvm-project-15.0.7/clang/test/Sema/
H A Dwarn-cast-function-type.c10 typedef int (f6)(long, int); typedef
18 f6 *f;
27 …f = (f6 *)x; /* expected-warning {{cast from 'int (*)(long)' to 'f6 *' (aka 'int (*)(long, int)') … in foo()
/llvm-project-15.0.7/clang/test/CodeGenCXX/
H A Dvisibility-inlines-hidden.cpp12 virtual void f6() { } in f6() function
24 virtual void f6() { } in f6() function
49 x0->X0::f6(); in use()
61 x1->X1::f6(); in use()
/llvm-project-15.0.7/llvm/test/MC/Mips/micromips/
H A Dvalid.s100 abs.d $f4, $f6 # CHECK: abs.d $f4, $f6 # encoding: [0x54,0x86,0x23,0x7b]
338 c.ngt.d $fcc4, $f24, $f6 # CHECK: c.ngt.d $fcc4, $f24, $f6 # encoding: [0x54,0xd8,0x87,0xfc]
344 c.seq.d $fcc4, $f30, $f6 # CHECK: c.seq.d $fcc4, $f30, $f6 # encoding: [0x54,0xde,0x86,0xbc]
352 c.ult.d $fcc6, $f6, $f16 # CHECK: c.ult.d $fcc6, $f6, $f16 # encoding: [0x56,0x06,0xc5,0x7c]
380 add.s $f4, $f6, $f8 # CHECK: add.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0x30]
382 sub.s $f4, $f6, $f8 # CHECK: sub.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0x70]
384 mul.s $f4, $f6, $f8 # CHECK: mul.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0xb0]
386 div.s $f4, $f6, $f8 # CHECK: div.s $f4, $f6, $f8 # encoding: [0x55,0x06,0x20,0xf0]
388 add.d $f4, $f6, $f8 # CHECK: add.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0x30]
390 sub.d $f4, $f6, $f8 # CHECK: sub.d $f4, $f6, $f8 # encoding: [0x55,0x06,0x21,0x70]
[all …]

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