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/llvm-project-15.0.7/llvm/test/MC/Mips/
H A Dmips64-alu-instructions.s68 # CHECK: dadd $9, $6, $7 # encoding: [0x2c,0x48,0xc7,0x00]
93 dadd $9,$6,$7
94 dadd $9,$6,17767
120 # CHECK: dadd $9, $9, $3 # encoding: [0x2c,0x48,0x23,0x01]
131 dadd $9, $3
133 dadd $9, 10
H A Dset-arch.s10 dadd $2, $2, $2
44 dadd $2, $2, $2
51 # CHECK: dadd $2, $2, $2
73 # CHECK: dadd $2, $2, $2
H A Dset-mips0-directive.s13 dadd $4, $4, $4
25 # CHECK: dadd $4, $4, $4
H A Dset-mips-directives.s11 dadd $2,$2,$2
47 # CHECK: dadd $2, $2, $2
H A Dmips_directives.s72 # CHECK: dadd $3, $3, $3
74 dadd $3, $3, $3 # encoding: [0x00,0x62,0x18,0x2c]
H A Dset-mips-directives-bad.s13 dadd $2,$2,$2 # CHECK: error: instruction requires a CPU feature not currently enabled
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl/
H A Dtsan_rtl_mips64.S27 dadd $a0,$zero,$sp
79 dadd $a0,$zero,$sp
132 dadd $a0,$zero,$sp
186 dadd $a0,$zero,$sp
/llvm-project-15.0.7/compiler-rt/lib/tsan/rtl-old/
H A Dtsan_rtl_mips64.S27 dadd $a0,$zero,$sp
79 dadd $a0,$zero,$sp
132 dadd $a0,$zero,$sp
186 dadd $a0,$zero,$sp
/llvm-project-15.0.7/llvm/test/MC/MSP430/
H A Dopcode.s20 dadd.b r7, r8 ; CHECK-INST: dadd.b r7, r8
46 dadd r7, r8 ; CHECK-INST: dadd r7, r8
/llvm-project-15.0.7/clang/test/CodeGen/
H A Darm-float-helpers.c84 double dadd(double a, double b) { return a + b; } in dadd() function
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dbfloat.ll76 %dadd = fpext bfloat %add to double
77 store double %dadd, ptr %pc
103 %dadd = fpext bfloat %add to double
104 ret double %dadd
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r6/
H A Dinvalid-mips64.s14 …dadd $sp,$s4,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
15 …dadd $sp,-27705 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fe…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips3/
H A Dvalid.s72 dadd $s3,$at,$ra
73 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
74 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64/
H A Dvalid.s106 dadd $s3,$at,$ra
107 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
108 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips4/
H A Dvalid.s104 dadd $s3,$at,$ra
105 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
106 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips5/
H A Dvalid.s104 dadd $s3,$at,$ra
105 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
106 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r3/
H A Dvalid.s112 dadd $s3,$at,$ra
113 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
114 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r2/
H A Dvalid.s113 dadd $s3,$at,$ra
114 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
115 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips64r5/
H A Dvalid.s112 dadd $s3,$at,$ra
113 … dadd $sp,$s4,-27705 # CHECK: daddi $sp, $20, -27705 # encoding: [0x62,0x9d,0x93,0xc7]
114 … dadd $sp,-27705 # CHECK: daddi $sp, $sp, -27705 # encoding: [0x63,0xbd,0x93,0xc7]
/llvm-project-15.0.7/llvm/test/MC/Mips/mips2/
H A Dinvalid-mips3.s14 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU fea…
H A Dinvalid-mips4.s16 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU featur…
/llvm-project-15.0.7/llvm/test/MC/Mips/mips1/
H A Dinvalid-mips3.s18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
H A Dinvalid-mips4.s18 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
H A Dinvalid-mips5.s22 …dadd $s3,$at,$ra # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feat…
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfloat-helpers.s318 define double @dadd(double %a, double %b) #0 {
319 ; CHECK-SOFT-LABEL: dadd:
326 ; CHECK-SOFTFP-LABEL: dadd:
333 ; CHECK-HARDFP-DP-LABEL: dadd:
337 ; CHECK-HARDFP-SPONLY-LABEL: dadd:

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