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Searched refs:createRegister (Results 1 – 18 of 18) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUArgumentUsageInfo.cpp156 = ArgDescriptor::createRegister(AMDGPU::SGPR0_SGPR1_SGPR2_SGPR3); in fixedABILayout()
157 AI.DispatchPtr = ArgDescriptor::createRegister(AMDGPU::SGPR4_SGPR5); in fixedABILayout()
158 AI.QueuePtr = ArgDescriptor::createRegister(AMDGPU::SGPR6_SGPR7); in fixedABILayout()
162 AI.ImplicitArgPtr = ArgDescriptor::createRegister(AMDGPU::SGPR8_SGPR9); in fixedABILayout()
163 AI.DispatchID = ArgDescriptor::createRegister(AMDGPU::SGPR10_SGPR11); in fixedABILayout()
166 AI.WorkGroupIDX = ArgDescriptor::createRegister(AMDGPU::SGPR12); in fixedABILayout()
167 AI.WorkGroupIDY = ArgDescriptor::createRegister(AMDGPU::SGPR13); in fixedABILayout()
168 AI.WorkGroupIDZ = ArgDescriptor::createRegister(AMDGPU::SGPR14); in fixedABILayout()
169 AI.LDSKernelId = ArgDescriptor::createRegister(AMDGPU::SGPR15); in fixedABILayout()
172 AI.WorkItemIDX = ArgDescriptor::createRegister(AMDGPU::VGPR31, Mask); in fixedABILayout()
[all …]
H A DSIMachineFunctionInfo.cpp96 ArgDescriptor::createRegister(ScratchRSrcReg); in SIMachineFunctionInfo()
179 ArgDescriptor::createRegister(AMDGPU::SGPR5); in SIMachineFunctionInfo()
219 ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addPrivateSegmentBuffer()
226 ArgInfo.DispatchPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchPtr()
233 ArgInfo.QueuePtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addQueuePtr()
241 = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addKernargSegmentPtr()
248 ArgInfo.DispatchID = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addDispatchID()
255 ArgInfo.FlatScratchInit = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addFlatScratchInit()
262 ArgInfo.ImplicitBufferPtr = ArgDescriptor::createRegister(TRI.getMatchingSuperReg( in addImplicitBufferPtr()
269 ArgInfo.LDSKernelId = ArgDescriptor::createRegister(getNextUserSGPR()); in addLDSKernelId()
H A DSIMachineFunctionInfo.h625 ArgInfo.WorkGroupIDX = ArgDescriptor::createRegister(getNextSystemSGPR());
631 ArgInfo.WorkGroupIDY = ArgDescriptor::createRegister(getNextSystemSGPR());
637 ArgInfo.WorkGroupIDZ = ArgDescriptor::createRegister(getNextSystemSGPR());
643 ArgInfo.WorkGroupInfo = ArgDescriptor::createRegister(getNextSystemSGPR());
663 = ArgDescriptor::createRegister(getNextSystemSGPR());
669 ArgInfo.PrivateSegmentWaveByteOffset = ArgDescriptor::createRegister(Reg);
H A DAMDGPUArgumentUsageInfo.h44 static constexpr ArgDescriptor createRegister(Register Reg,
H A DAMDGPUTargetMachine.cpp1554 Arg = ArgDescriptor::createRegister(Reg); in parseMachineFunctionInfo()
H A DSIISelLowering.cpp1891 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialEntryInputVGPRs()
1897 Info.setWorkItemIDY(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1904 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1911 Info.setWorkItemIDZ(ArgDescriptor::createRegister(AMDGPU::VGPR0, in allocateSpecialEntryInputVGPRs()
1918 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg)); in allocateSpecialEntryInputVGPRs()
1949 return ArgDescriptor::createRegister(Reg, Mask); in allocateVGPR32Input()
1966 return ArgDescriptor::createRegister(Reg); in allocateSGPR32InputImpl()
2028 Info.setWorkItemIDX(ArgDescriptor::createRegister(Reg, Mask)); in allocateSpecialInputVGPRsFixed()
2029 Info.setWorkItemIDY(ArgDescriptor::createRegister(Reg, Mask << 10)); in allocateSpecialInputVGPRsFixed()
2030 Info.setWorkItemIDZ(ArgDescriptor::createRegister(Reg, Mask << 20)); in allocateSpecialInputVGPRsFixed()
/llvm-project-15.0.7/llvm/lib/CodeGen/AsmPrinter/
H A DDwarfExpression.cpp104 DwarfRegs.push_back(Register::createRegister(-1, nullptr)); in addMachineReg()
114 DwarfRegs.push_back(Register::createRegister(Reg, nullptr)); in addMachineReg()
126 DwarfRegs.push_back(Register::createRegister(Reg, "super-register")); in addMachineReg()
166 DwarfRegs.push_back(Register::createRegister(Reg, "sub-register")); in addMachineReg()
H A DDwarfExpression.h115 static Register createRegister(int RegNo, const char *Comment) { in createRegister() function
/llvm-project-15.0.7/bolt/lib/Passes/
H A DRegReAssign.cpp84 Inst, MCCFIInstruction::createRegister( in swap()
91 Inst, MCCFIInstruction::createRegister( in swap()
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcFrameLowering.cpp168 MCCFIInstruction::createRegister(nullptr, regOutRA, regInRA)); in emitPrologue()
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCFIInstrInserter.cpp377 MCCFIInstruction::createRegister(nullptr, Reg, *RO.Reg)); in insertCFIInstrs()
/llvm-project-15.0.7/llvm/include/llvm/MC/
H A DMCDwarf.h585 static MCCFIInstruction createRegister(MCSymbol *L, unsigned Register1, in createRegister() function
/llvm-project-15.0.7/bolt/lib/Core/
H A DExceptions.cpp580 Offset, MCCFIInstruction::createRegister(nullptr, Instr.Ops[0], in fillCFIInfoFor()
H A DBinaryFunction.cpp709 setCFIFor(Instr, MCCFIInstruction::createRegister(nullptr, NewReg, in mutateCFIRegisterFor()
/llvm-project-15.0.7/llvm/lib/MC/
H A DMCStreamer.cpp661 MCCFIInstruction::createRegister(Label, Register1, Register2); in emitCFIRegister()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCFrameLowering.cpp1198 unsigned CFIRegister = MF.addFrameInst(MCCFIInstruction::createRegister( in emitPrologue()
/llvm-project-15.0.7/llvm/lib/CodeGen/MIRParser/
H A DMIParser.cpp2489 MF.addFrameInst(MCCFIInstruction::createRegister(nullptr, Reg, Reg2)); in parseCFIOperand()
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMBaseInstrInfo.cpp6505 MCCFIInstruction::createRegister(nullptr, DwarfLR, DwarfReg)); in emitCFIForLRSaveToReg()