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Searched refs:VROR (Results 1 – 7 of 7) sorted by relevance

/llvm-project-15.0.7/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvror.ll6 ;;; We test VROR*vl and VROR*vml instructions.
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp789 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg()
796 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg()
807 HalfV0 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {N, Sn}); in buildHvxVectorReg()
808 HalfV1 = DAG.getNode(HexagonISD::VROR, dl, VecTy, {M, Sm}); in buildHvxVectorReg()
905 Vec = DAG.getNode(HexagonISD::VROR, dl, ByteTy, Vec, S4); in createHvxPrefixPred()
1251 SingleV = DAG.getNode(HexagonISD::VROR, dl, SingleTy, SingleV, IdxV); in insertHvxSubvectorReg()
1265 SingleV = DAG.getNode(HexagonISD::VROR, dl, SingleTy, SingleV, in insertHvxSubvectorReg()
1555 Res = DAG.getNode(HexagonISD::VROR, dl, ByteTy, Res, S); in LowerHvxConcatVectors()
2623 case HexagonISD::VROR: { in PerformHvxDAGCombine()
2624 if (Ops[0].getOpcode() == HexagonISD::VROR) { in PerformHvxDAGCombine()
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H A DHexagonISelLowering.h65 VROR, enumerator
H A DHexagonISelDAGToDAG.cpp911 case HexagonISD::VROR: return SelectHvxRor(N); in Select()
H A DHexagonISelLowering.cpp1905 case HexagonISD::VROR: return "HexagonISD::VROR"; in getTargetNodeName()
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVVPInstrPatternsVec.td620 defm: Reduce_GenericInt<VectorVT, ResRC, ResVT, "or", "VROR">;
H A DVEInstrVec.td1396 // Section 8.14.8 - VROR (Vector Reduction Or)
1397 defm VROR : RVF1m<"vror", 0x98, V64, VM>;