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/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dspill-wide-sgpr.ll6 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 0
7 ; VGPR: v_writelane_b32 v{{[0-9]+}}, s{{[0-9]+}}, 1
8 ; VGPR: s_cbranch_scc1
10 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 0
11 ; VGPR: v_readlane_b32 s{{[0-9]+}}, v{{[0-9]+}}, 1
36 ; VGPR: s_cbranch_scc1
66 ; VGPR: s_cbranch_scc1
98 ; VGPR: s_cbranch_scc1
134 ; VGPR: s_cbranch_scc1
180 ; VGPR: s_cbranch_scc1
[all …]
H A Dframe-setup-without-sgpr-to-vgpr-spills.ll11 ; SPILL-TO-VGPR: ; %bb.0:
15 ; SPILL-TO-VGPR-NEXT: s_mov_b64 exec, s[4:5]
17 ; SPILL-TO-VGPR-NEXT: s_mov_b32 s33, s32
18 ; SPILL-TO-VGPR-NEXT: s_addk_i32 s32, 0x400
20 ; SPILL-TO-VGPR-NEXT: v_mov_b32_e32 v0, 0
23 ; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
24 ; SPILL-TO-VGPR-NEXT: s_getpc_b64 s[4:5]
35 ; SPILL-TO-VGPR-NEXT: s_waitcnt vmcnt(0)
36 ; SPILL-TO-VGPR-NEXT: s_setpc_b64 s[30:31]
39 ; NO-SPILL-TO-VGPR: ; %bb.0:
[all …]
H A Dcollapse-endcf.ll35 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[INNER_SPILL_LANE_0]]
36 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[INNER_SPILL_LANE_1]]
39 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[OUTER_SPILL_LANE_0]]
40 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[OUTER_SPILL_LANE_1]]
101 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[OUTER_SPILL_LANE_0]]
102 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[OUTER_SPILL_LANE_1]]
106 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[INNER_SPILL_LANE_0]]
107 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[INNER_SPILL_LANE_1]]
177 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[THEN_SPILL_LANE_0]]
366 ; GCN-O0-DAG: v_readlane_b32 s{{[0-9]+}}, [[VGPR]], [[SPILL_LANE_0]]
[all …]
H A Dfold-fi-operand-shrink.mir6 # First operand is FI is in a VGPR, other operand is a VGPR
31 # First operand is a VGPR, other operand FI is in a VGPR
56 # First operand is FI is in an SGPR, other operand is a VGPR
81 # First operand is an SGPR, other operand FI is in a VGPR
106 # First operand is FI is in an SGPR, other operand is a VGPR
131 # First operand is a VGPR, other operand FI is in an SGPR
156 # First operand is FI is in a VGPR, other operand is an inline imm in a VGPR
177 # First operand is an inline imm in a VGPR, other operand FI is in a VGPR
198 # First operand is FI is in a VGPR, other operand is an literal constant in a VGPR
219 # First operand is a literal constant in a VGPR, other operand FI is in a VGPR
H A Dcontrol-flow-fastregalloc.ll8 ; FIXME: This checks with SGPR to VGPR spilling disabled, but this may
13 ; VGPR: workitem_private_segment_byte_size = 12{{$}}
26 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
27 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
52 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
53 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_HI:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_HI_LANE]]
85 ; VGPR: workitem_private_segment_byte_size = 16{{$}}
98 ; VGPR: v_writelane_b32 [[SPILL_VGPR:v[0-9]+]], s[[SAVEEXEC_LO]], [[SAVEEXEC_LO_LANE:[0-9]+]]
99 ; VGPR: v_writelane_b32 [[SPILL_VGPR]], s[[SAVEEXEC_HI]], [[SAVEEXEC_HI_LANE:[0-9]+]]
124 ; VGPR: v_readlane_b32 s[[S_RELOAD_SAVEEXEC_LO:[0-9]+]], [[SPILL_VGPR]], [[SAVEEXEC_LO_LANE]]
[all …]
H A Dillegal-sgpr-to-vgpr-copy.ll4 … error: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
13 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
21 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v4i32 void (): illegal SGPR to VGPR copy
29 …rror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v8i32 void (): illegal SGPR to VGPR copy
37 …ror: <unknown>:0:0: in function illegal_vgpr_to_sgpr_copy_v16i32 void (): illegal SGPR to VGPR copy
45 … error: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_i32 void (): illegal SGPR to VGPR copy
54 …rror: <unknown>:0:0: in function illegal_agpr_to_sgpr_copy_v2i32 void (): illegal SGPR to VGPR copy
H A Dlo16-hi16-illegal-copy.mir10 … error: <unknown>:0:0: in function lo_to_lo_illegal_vgpr_to_sgpr void (): illegal SGPR to VGPR copy
35 … error: <unknown>:0:0: in function lo_to_lo_illegal_agpr_to_sgpr void (): illegal SGPR to VGPR copy
H A Duse-sgpr-multiple-times.ll143 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
145 ; GCN: v_fma_f32 [[RESULT0:v[0-9]+]], [[SK]], [[SK]], [[VGPR]]
173 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
175 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
203 ; GCN-DAG: v_mov_b32_e32 [[VGPR:v[0-9]+]], [[SGPR]]
205 ; GCN: v_fma_f32 [[RESULT:v[0-9]+]], [[VGPR]], [[SK]], [[SK]]
H A Dspill-scavenge-offset.ll10 ; When the offset of VGPR spills into scratch space gets too large, an additional SGPR
33 ; mark most VGPR registers as used to increase register pressure
128 ; load VGPR data
154 ; mark most VGPR registers as used to increase register pressure
H A Dadd_i64.ll20 ; Check that the SGPR add operand is correctly moved to a VGPR.
31 ; Swap the arguments. Check that the SGPR -> VGPR copy works with the
H A Dcallee-frame-setup.ll128 ; There is stack usage only because of the need to evict a VGPR for
265 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
311 ; Use a copy to a free SGPR instead of introducing a second CSR VGPR.
418 ; Use all clobberable registers, so FP has to spill to a VGPR.
428 ; Need a new CSR VGPR to satisfy the FP spill.
457 ; Use all clobberable registers, so FP has to spill to a VGPR.
474 ; register is needed to access the CSR VGPR slot.
506 ; Use all clobberable registers, so FP has to spill to a VGPR.
513 ; Use all clobberable VGPRs, so a CSR spill is needed for the VGPR
580 ; VGPR.
[all …]
H A Dcall-alias-register-usage1.ll9 ; The parent kernel has a higher VGPR usage than the possible callees.
H A Dsgpr-copy-duplicate-operand.ll4 ; Copy VGPR -> SGPR used twice as an instruction operand, which is then
H A Dglobal-load-saddr-to-vaddr.ll4 ; The first load produces address in a VGPR which is used in address calculation
7 ; vector registers because it all starts with a VGPR produced by the entry block
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DAMDGPUCallingConv.td136 (sequence "VGPR%u", 56, 63),
137 (sequence "VGPR%u", 72, 79),
138 (sequence "VGPR%u", 88, 95),
139 (sequence "VGPR%u", 104, 111),
140 (sequence "VGPR%u", 120, 127),
141 (sequence "VGPR%u", 136, 143),
142 (sequence "VGPR%u", 152, 159),
143 (sequence "VGPR%u", 168, 175),
144 (sequence "VGPR%u", 184, 191),
145 (sequence "VGPR%u", 200, 207),
[all …]
H A DSIRegisterInfo.td311 // VGPR registers
313 defm VGPR#Index :
543 // VGPR 32-bit registers
553 // VGPR 64-bit registers
556 // VGPR 96-bit registers
559 // VGPR 128-bit registers
562 // VGPR 160-bit registers
565 // VGPR 192-bit registers
568 // VGPR 224-bit registers
571 // VGPR 256-bit registers
[all …]
H A DSIRegisterInfo.h55 Register VGPR; member
59 SpilledReg(Register R, int L) : VGPR(R), Lane(L) {} in SpilledReg()
62 bool hasReg() { return VGPR != 0; } in hasReg()
H A DAMDGPURegisterBanks.td13 def VGPRRegBank : RegisterBank<"VGPR",
/llvm-project-15.0.7/llvm/docs/AMDGPU/
H A Dgfx1013_vaddr_cdc744.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes w…
H A Dgfx1030_vaddr_cdc744.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes w…
H A Dgfx10_vaddr_cdc744.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 1-13 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 1-8 dwords. Opcodes w…
H A Dgfx1013_vaddr_49d53a.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes whi…
H A Dgfx1030_vaddr_49d53a.rst15 …and may be specified using either :ref:`standard VGPR syntax<amdgpu_synid_v>` or special :ref:`NSA…
19 * If specified using :ref:`NSA VGPR syntax<amdgpu_synid_nsa>`, the size is 8-12 dwords.
20 * If specified using :ref:`standard VGPR syntax<amdgpu_synid_v>`, the size is 8 dwords. Opcodes whi…
/llvm-project-15.0.7/llvm/include/llvm/IR/
H A DIntrinsicsAMDGPU.td999 [data_ty, // vdata(VGPR)
1049 [data_ty, // vdata(VGPR)
1064 [data_ty, // vdata(VGPR)
1103 [LLVMMatchType<0>, // src(VGPR)
1104 LLVMMatchType<0>, // cmp(VGPR)
1139 [LLVMMatchType<0>, // src(VGPR)
1140 LLVMMatchType<0>, // cmp(VGPR)
1178 llvm_i32_ty, // vindex(VGPR)
1276 [llvm_i32_ty, // src(VGPR)
1277 llvm_i32_ty, // cmp(VGPR)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dregbankselect-amdgcn.s.buffer.load.mir5 # We see the offset is a VGPR, but this is due to a constant for some
6 # reason ending up in a VGPR. This shouldn't really ever happen, but

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