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Searched refs:VCVT (Results 1 – 20 of 20) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dfp-armv8.s3 @ VCVT{B,T}
26 @ VCVT{A,N,P,M}
H A Dthumb-fp-armv8.s3 @ VCVT{B,T}
29 @ VCVT{A,N,P,M}
H A Dfp-armv8-m.s6 @ VCVT{B,T}
33 @ VCVT{A,N,P,M}
H A Dinvalid-fp-armv8.s3 @ VCVT{B,T}
H A Dsimple-fp-encoding.s367 @ VCVT (between floating-point and fixed-point)
/llvm-project-15.0.7/llvm/test/MC/Disassembler/ARM/
H A Dfullfp16-neon-thumb.txt269 # space of the new FP16 VCVT(between floating - point and fixed - point,
271 # 1 -- VCVT op
272 # 2 -- VCVT FP size
H A Dfullfp16-neon-arm.txt269 # space of the new FP16 VCVT(between floating - point and fixed - point,
273 # 1 -- VCVT op
274 # 2 -- VCVT FP size
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMScheduleA57.td734 "VCVT(A|N|P|M)(SH|UH|SS|US|SD|UD)", "VCVT(BDH|THD|TDH)")>;
1161 "VCVT(f2sd|f2ud|s2fd|u2fd|f2sq|f2uq|s2fq|u2fq|f2xsd|f2xud|xs2fd|xu2fd)",
1162 "VCVT(f2xsq|f2xuq|xs2fq|xu2fq)",
1163 "VCVT(AN|MN|NN|PN)(SDf|SQf|UDf|UQf|SDh|SQh|UDh|UQh)")>;
1167 "VCVT(h2sd|h2ud|s2hd|u2hd|h2sq|h2uq|s2hq|u2hq|h2xsd|h2xud|xs2hd|xu2hd)",
1168 "VCVT(h2xsq|h2xuq|xs2hq|xu2hq)",
1169 "VCVT(f2h|h2f)")>;
H A DARMScheduleR52.td796 (instregex "VCVT", "VSITO", "VUITO", "VTO")>;
H A DARMScheduleSwift.td623 def : InstRW<[SwiftWriteP1FourCycle], (instregex "VCVT", "V(S|U)IT", "VTO(S|U)")>;
H A DARMInstrNEON.td6782 // VCVT : Vector Convert Between Floating-Point and Integers
6827 // VCVT{A, N, P, M}
6859 // VCVT : Vector Convert Between Floating-Point and Fixed-Point.
6939 // VCVT : Vector Convert Between Half-Precision and Single-Precision.
H A DARMInstrVFP.td131 // The VCVT to/from fixed-point instructions encode the 'fbits' operand
H A DARMISelLowering.cpp8002 if (SDValue VCVT = LowerBuildVectorOfFPTrunc(Op, DAG, Subtarget)) in LowerBUILD_VECTOR() local
8003 return VCVT; in LowerBUILD_VECTOR()
8004 if (SDValue VCVT = LowerBuildVectorOfFPExt(Op, DAG, Subtarget)) in LowerBUILD_VECTOR() local
8005 return VCVT; in LowerBUILD_VECTOR()
H A DARMInstrMVE.td4066 // The unsuffixed VCVT for float->int implicitly rounds toward zero,
4072 // Whereas VCVT for int->float rounds to nearest
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86SchedSkylakeServer.td1903 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1904 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1905 "VCVT(T?)PS2DQYrm",
1906 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1907 "VCVT(T?)PS2QQZ256rm(b?)",
1908 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1909 "VCVT(T?)PS2UQQZ256rm(b?)",
2005 def: InstRW<[SKXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2006 "VCVT(T?)SS2USI64Zrm(b?)")>;
2013 def: InstRW<[SKXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
[all …]
H A DX86SchedIceLake.td1922 "VCVT(T?)PD2QQ(Z|Z256)rm(b?)",
1923 "VCVT(T?)PD2UQQ(Z|Z256)rm(b?)",
1924 "VCVT(T?)PS2DQYrm",
1925 "VCVT(T?)PS2DQ(Z|Z256)rm(b?)",
1926 "VCVT(T?)PS2QQZ256rm(b?)",
1927 "VCVT(T?)PS2UDQ(Z|Z256)rm(b?)",
1928 "VCVT(T?)PS2UQQZ256rm(b?)",
2024 def: InstRW<[ICXWriteResGroup176], (instregex "VCVT(T?)SD2USIZrm(b?)",
2025 "VCVT(T?)SS2USI64Zrm(b?)")>;
2032 def: InstRW<[ICXWriteResGroup177], (instregex "VCVT(T?)PS2QQZrm(b?)",
[all …]
H A DX86ScheduleZnver1.td1285 def : InstRW<[ZnWriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
1287 def : InstRW<[ZnWriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
H A DX86ScheduleZnver2.td1299 def : InstRW<[Zn2WriteCVTPD2DQr], (instregex "VCVT(T?)PD2DQYrr")>;
1301 def : InstRW<[Zn2WriteCVTPD2DQLd], (instregex "VCVT(T?)PD2DQYrm")>;
/llvm-project-15.0.7/llvm/test/CodeGen/VE/VELIntrinsics/
H A Dvcvt.ll6 ;;; We test VCVT*vl, VCVT*vl_v, VCVT*vml_v, PVCVT*vl, PVCVT*vl_v, and
/llvm-project-15.0.7/llvm/test/CodeGen/ARM/
H A Dfp16-instructions.ll222 ; 5. VCVT (between floating-point and fixed-point)
225 ; 6. VCVT (between floating-point and integer, both directions)