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Searched refs:SIEncodingFamily (Results 1 – 17 of 17) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DEXPInstructions.td30 : EXPCommon<row, done>, SIMCInstr<NAME, SIEncodingFamily.NONE> {
69 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.SI>, EXPe_ComprVM {
83 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.VI>, EXPe_vi {
98 : EXP_Real_ComprVM<_done, pseudo, SIEncodingFamily.GFX10>, EXPe_ComprVM {
112 : EXP_Real_Row<_row, _done, pseudo, SIEncodingFamily.GFX11>, EXPe_Row {
H A DVOP2Instructions.td1108 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX11>,
1143 VOP2_Real<ps, SIEncodingFamily.GFX11, asmName>,
1154 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1166 SIEncodingFamily.GFX11> {
1185 VOP2_Real<ps, SIEncodingFamily.GFX11>,
1351 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1686 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1691 VOP2_Real<!cast<VOP2_Pseudo>(NAME), SIEncodingFamily.SI>,
1830 VOP2_Real<!cast<VOP2_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
1836 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
[all …]
H A DVOP3Instructions.td968 VOP3_Real<!cast<VOP_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
973 VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.GFX10>,
988 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX10>,
993 VOP3_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX10>,
1101 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1106 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1129 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1134 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
1214 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
1236 def _vi : VOP3_Real<!cast<VOP_Pseudo>(NAME), SIEncodingFamily.VI>,
[all …]
H A DVOP1Instructions.td641 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX11>,
647 VOP1_Real<ps, SIEncodingFamily.GFX11>,
660 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX11>,
742 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.GFX10>,
825 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
830 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
859 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.SI>,
864 VOP3_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.SI>,
957 VOP1_Real<!cast<VOP1_Pseudo>(NAME), SIEncodingFamily.VI>,
965 VOP1_Real<!cast<VOP1_Pseudo>(NAME#"_e32"), SIEncodingFamily.VI>,
[all …]
H A DLDSDIRInstructions.td65 SIMCInstr<opName, SIEncodingFamily.NONE> {
109 def _gfx11 : LDSDIR_Real<op, lds, SIEncodingFamily.GFX11> {
H A DVOPInstructions.td58 SIMCInstr <opName#suffix, SIEncodingFamily.NONE> {
549 SIMCInstr <opName#"_sdwa", SIEncodingFamily.NONE> {
583 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA> {
648 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SDWA9>;
765 SIMCInstr <OpName#"_dpp", SIEncodingFamily.NONE> {
1329 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1333 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1342 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1353 VOP3_Real<ps, SIEncodingFamily.GFX11>,
1358 VOP3_Real<ps, SIEncodingFamily.GFX11>,
[all …]
H A DVOPCInstructions.td108 SIMCInstr<opName#"_e32", SIEncodingFamily.NONE> {
1187 def _e32_gfx11 : VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1189 def _e64_gfx11 : VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1277 VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name#"_e32">,
1281 VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
1374 VOPC_Real<ps32, SIEncodingFamily.GFX11>,
1380 VOP3_Real<ps64, SIEncodingFamily.GFX11>,
1413 SIMCInstr<psDPP.PseudoInstr, SIEncodingFamily.GFX11> {
1434 : VOPC_Real<ps32, SIEncodingFamily.GFX11, asm_name>,
1441 : VOP3_Real<ps64, SIEncodingFamily.GFX11, asm_name>,
[all …]
H A DVOP3PInstructions.td896 SIEncodingFamily.GFX11, asmName>,
905 SIEncodingFamily.GFX11> {
952 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.VI>,
961 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
975 def _gfx90a_acd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.GFX90A>,
978 …def _gfx90a_vcd : VOP3P_Real<!cast<VOP3_Pseudo>(NAME # "_vgprcd" # "_e64"), SIEncodingFamily.GFX90…
1009 def _gfx940_acd : VOP3P_Real<PS_ACD, SIEncodingFamily.GFX940>,
1012 def _gfx940_vcd : VOP3P_Real<PS_VCD, SIEncodingFamily.GFX940>,
1025 def _vi : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
1034 def _gfx940 : VOP3P_Real<!cast<VOP3_Pseudo>(NAME#"_e64"), SIEncodingFamily.VI>,
[all …]
H A DSIInstrInfo.td20 // SIEncodingFamily enum in SIInstrInfo.cpp and the columns of the
22 def SIEncodingFamily {
2704 SIMCInstr<opName, SIEncodingFamily.NONE> {
2721 SIMCInstr<opName, SIEncodingFamily.VI> {
2821 let KeyCol = [!cast<string>(SIEncodingFamily.NONE)];
2823 let ValueCols = [[!cast<string>(SIEncodingFamily.SI)],
2824 [!cast<string>(SIEncodingFamily.VI)],
2825 [!cast<string>(SIEncodingFamily.SDWA)],
2826 [!cast<string>(SIEncodingFamily.SDWA9)],
2831 [!cast<string>(SIEncodingFamily.GFX80)],
[all …]
H A DSMInstructions.td33 SIMCInstr<opName, SIEncodingFamily.NONE> {
483 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
532 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.VI>
587 int Subtarget = SIEncodingFamily.GFX9;
819 , SIMCInstr<ps.PseudoInstr, SIEncodingFamily.SI>
997 : SMEM_Real_10Plus_common<op, ps, ps.Mnemonic, SIEncodingFamily.GFX10,
1200 SMEM_Real_10Plus_common<op, ps, opName, SIEncodingFamily.GFX11,
H A DBUFInstructions.td57 SIMCInstr<opName, SIEncodingFamily.NONE> {
292 SIMCInstr<opName, SIEncodingFamily.NONE> {
2099 Base_MUBUF_Real_gfx6_gfx7_gfx10<op{6-0}, ps, SIEncodingFamily.SI> {
2604 Base_MTBUF_Real_gfx6_gfx7_gfx10<op{2-0}, ps, SIEncodingFamily.SI> {
2665 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.VI, has_sccb> {
2674 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX90A, has_sccb> {
2684 MUBUF_Real_Base_vi<op, ps, SIEncodingFamily.GFX940> {
2740 SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX80> {
2912 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.VI> {
2920 MTBUF_Real_Base_vi <op, ps, SIEncodingFamily.GFX90A> {
[all …]
H A DVINTERPInstructions.td170 VINTERP_Real<!cast<VOP3_Pseudo>(NAME), SIEncodingFamily.GFX11>,
H A DDSInstructions.td11 SIMCInstr <opName, SIEncodingFamily.NONE> {
1189 SIEncodingFamily.GFX11>;
1193 …def _gfx11 : Base_DS_Real_gfx6_gfx7_gfx10_gfx11<op, backing_pseudo, SIEncodingFamily.GFX11, real_n…
1261 SIEncodingFamily.GFX10>;
1296 SIEncodingFamily.SI>;
1322 SIEncodingFamily.SI>;
1484 SIMCInstr <ps.Mnemonic, SIEncodingFamily.VI> {
H A DVOPDInstructions.td61 SIMCInstr<NAME, SIEncodingFamily.GFX11> {
H A DSIInstrInfo.cpp7859 enum SIEncodingFamily { enum
7879 return SIEncodingFamily::SI; in subtargetEncodingFamily()
7882 return SIEncodingFamily::VI; in subtargetEncodingFamily()
7884 return SIEncodingFamily::GFX10; in subtargetEncodingFamily()
7886 return SIEncodingFamily::GFX11; in subtargetEncodingFamily()
7912 SIEncodingFamily Gen = subtargetEncodingFamily(ST); in pseudoToMCOpcode()
7916 Gen = SIEncodingFamily::GFX9; in pseudoToMCOpcode()
7922 Gen = SIEncodingFamily::GFX80; in pseudoToMCOpcode()
7927 Gen = SIEncodingFamily::SDWA; in pseudoToMCOpcode()
7930 Gen = SIEncodingFamily::SDWA9; in pseudoToMCOpcode()
[all …]
H A DSOPInstructions.td25 SIMCInstr<opName, SIEncodingFamily.NONE> {
718 SIMCInstr<opName, SIEncodingFamily.NONE> {
1479 class Select_gfx11<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX11> {
1484 class Select_gfx10<string opName> : SIMCInstr<opName, SIEncodingFamily.GFX10> {
1489 class Select_vi<string opName> : SIMCInstr<opName, SIEncodingFamily.VI> {
1494 class Select_gfx6_gfx7<string opName> : SIMCInstr<opName, SIEncodingFamily.SI> {
H A DFLATInstructions.td24 SIMCInstr<opName, SIEncodingFamily.NONE> {
1559 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.SI> {
1627 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.VI> {
1644 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX940> {
1899 FLAT_Real<op, ps>, SIMCInstr<ps.PseudoInstr, SIEncodingFamily.GFX10> {
2135 SIMCInstr <ps.PseudoInstr, SIEncodingFamily.GFX11> {