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Searched refs:SHR (Results 1 – 25 of 84) sorted by relevance

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/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/
H A Dsub-lshr-or-to-icmp-select.ll9 ; CHECK-NEXT: [[SHR:%.*]] = zext i1 [[TMP1]] to i32
10 ; CHECK-NEXT: ret i32 [[SHR]]
24 ; CHECK-NEXT: [[SHR:%.*]] = zext i1 [[TMP1]] to i32
25 ; CHECK-NEXT: ret i32 [[SHR]]
39 ; CHECK-NEXT: [[SHR:%.*]] = zext <4 x i1> [[TMP1]] to <4 x i32>
40 ; CHECK-NEXT: ret <4 x i32> [[SHR]]
53 ; CHECK-NEXT: ret <4 x i32> [[SHR]]
68 ; CHECK-NEXT: [[SHR:%.*]] = zext i1 [[TMP1]] to i32
70 ; CHECK-NEXT: ret i32 [[SHR]]
85 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[OR]], 31
[all …]
H A Dsub-ashr-or-to-icmp-select.ll77 ; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i32
78 ; CHECK-NEXT: ret i32 [[SHR]]
119 ; CHECK-NEXT: ret i32 [[SHR]]
158 ; CHECK-NEXT: ret <4 x i32> [[SHR]]
183 ; CHECK-NEXT: ret <4 x i32> [[SHR]]
229 ; CHECK-NEXT: ret i32 [[SHR]]
245 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
258 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 31
259 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[X]]
272 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[OR]], 31
[all …]
H A Dpr49688.ll9 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 7, [[I1]]
10 ; CHECK-NEXT: [[CMP4:%.*]] = icmp slt i32 [[SHR]], [[I1]]
26 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 7, [[H:%.*]]
27 ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt i32 [[SHR]], [[G]]
H A Dashr-lshr.ll442 ; CHECK-NEXT: ret i32 [[SHR]]
455 ; CHECK-NEXT: ret i32 [[SHR]]
468 ; CHECK-NEXT: ret i32 [[SHR]]
482 ; CHECK-NEXT: ret i32 [[SHR]]
494 ; CHECK-NEXT: ret <3 x i42> [[SHR]]
505 ; CHECK-NEXT: ret <3 x i42> [[SHR]]
516 ; CHECK-NEXT: ret i17 [[SHR]]
529 ; CHECK-NEXT: ret i17 [[SHR]]
542 ; CHECK-NEXT: ret i32 [[SHR]]
556 ; CHECK-NEXT: ret i32 [[SHR]]
[all …]
H A Dsub-ashr-and-to-icmp-select.ll164 ; CHECK-NEXT: [[SHR:%.*]] = sext i1 [[TMP1]] to i32
165 ; CHECK-NEXT: store i32 [[SHR]], i32* [[P:%.*]], align 4
166 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
179 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 7
180 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
192 ; CHECK-NEXT: [[SHR:%.*]] = ashr <4 x i32> [[SUB]], <i32 31, i32 31, i32 31, i32 undef>
193 ; CHECK-NEXT: [[AND:%.*]] = and <4 x i32> [[SHR]], [[X]]
205 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SUB]], 15
206 ; CHECK-NEXT: [[AND:%.*]] = and i32 [[SHR]], [[X]]
H A Dshift-shift.ll605 ; CHECK-NEXT: [[SHR:%.*]] = lshr i8 28, [[X:%.*]]
606 ; CHECK-NEXT: call void @use8(i8 [[SHR]])
622 ; CHECK-NEXT: [[SHR:%.*]] = lshr i8 28, [[X:%.*]]
623 ; CHECK-NEXT: [[SHL:%.*]] = shl nuw i8 [[SHR]], 3
637 ; CHECK-NEXT: [[SHR:%.*]] = lshr i8 60, [[X:%.*]]
638 ; CHECK-NEXT: [[SHL:%.*]] = shl i8 [[SHR]], 3
666 ; CHECK-NEXT: [[SHR:%.*]] = lshr <2 x i8> <i8 45, i8 45>, [[X:%.*]]
667 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 undef, i8 2>
682 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 2, i8 2>
697 ; CHECK-NEXT: [[SHL:%.*]] = shl <2 x i8> [[SHR]], <i8 1, i8 2>
[all …]
H A Drotate.ll192 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[X]], [[SUB]]
193 ; CHECK-NEXT: [[R:%.*]] = or i32 [[SHR]], [[SHL]]
209 ; CHECK-NEXT: [[SHR:%.*]] = lshr i37 [[X]], [[Y]]
210 ; CHECK-NEXT: [[R:%.*]] = or i37 [[SHR]], [[SHL]]
226 ; CHECK-NEXT: [[SHR:%.*]] = lshr i8 [[X]], [[Y]]
227 ; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], [[SHR]]
333 ; CHECK-NEXT: [[SHR:%.*]] = lshr i8 [[X]], [[YMASK]]
335 ; CHECK-NEXT: [[R:%.*]] = or i8 [[SHL]], [[SHR]]
507 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHR]], [[SHL]]
710 ; CHECK-NEXT: [[OR:%.*]] = or i33 [[SHL]], [[SHR]]
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/PhaseOrdering/
H A Dtwo-shifts-by-sext.ll34 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
35 ; CHECK-NEXT: ret i32 [[SHR]]
55 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
56 ; CHECK-NEXT: ret i32 [[SHR]]
79 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
80 ; CHECK-NEXT: ret i32 [[SHR]]
106 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[SHL]], [[CONV]]
107 ; CHECK-NEXT: ret i32 [[SHR]]
/llvm-project-15.0.7/llvm/test/Transforms/LoopIdiom/X86/
H A Dctlz.ll46 ; LZCNT-NEXT: [[SHR]] = ashr i32 [[SHR11]], 1
79 ; NOLZCNT-NEXT: [[SHR]] = ashr i32 [[SHR11]], 1
156 ; ALL-NEXT: [[SHR]] = ashr i32 [[N_ADDR_05]], 1
221 ; ALL-NEXT: [[SHR]] = lshr i32 [[N_ADDR_05]], 1
285 ; ALL-NEXT: [[SHR]] = ashr i32 [[N_ADDR_0]], 1
337 ; ALL-NEXT: [[SHR]] = lshr i32 [[N_ADDR_0]], 1
391 ; ALL-NEXT: [[SHR]] = ashr i32 [[N_ADDR_0]], 1
444 ; ALL-NEXT: [[SHR]] = lshr i32 [[N_ADDR_0]], 1
500 ; ALL-NEXT: [[SHR]] = ashr i32 [[N_ADDR_0]], 1
554 ; ALL-NEXT: [[SHR]] = lshr i32 [[N_ADDR_0]], 1
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dimmv216.ll128 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
129 ; VI-DAG: v_mov_b32_e32 [[V_SHR:v[0-9]+]], [[SHR]]
153 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
154 ; VI-DAG: v_mov_b32_e32 [[V_SHR:v[0-9]+]], [[SHR]]
178 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
179 ; VI-DAG: v_mov_b32_e32 [[V_SHR:v[0-9]+]], [[SHR]]
203 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
229 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
254 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
279 ; VI-DAG: s_lshr_b32 [[SHR:s[0-9]+]], [[VAL]], 16
[all …]
H A Dbfe-combine.ll10 ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 6, v{{[0-9]+}}
11 ; CI: v_and_b32_e32 v[[ADDRLO:[0-9]+]], 0x3fc, v[[SHR]]
33 ; CI: v_lshrrev_b32_e32 v[[SHR:[0-9]+]], 1, v{{[0-9]+}}
34 ; CI: v_and_b32_e32 v[[AND:[0-9]+]], 0x7fff8000, v[[SHR]]
H A Dalignbit-pat.ll4 ; GCN-DAG: s_load_dword s[[SHR:[0-9]+]]
6 ; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], s[[SHR]]
20 ; GCN-DAG: load_dword v[[SHR:[0-9]+]],
22 ; GCN: v_alignbit_b32 v{{[0-9]+}}, v[[HI]], v[[LO]], v[[SHR]]
H A Ddivergence-driven-buildvector.ll138 ; GCN: %[[SHR:[0-9]+]]:sreg_32 = S_LSHR_B32 killed %{{[0-9]+}}, killed %[[SHIFT]]
141 ; GCN: S_OR_B32 killed %[[SHR]], killed %[[AND]]
158 ; GCN: %[[SHR:[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 killed %{{[0-9]+}}, %0, implicit $exec
161 ; GCN: V_OR_B32_e64 killed %[[SHR]], killed %[[AND]], implicit $exec
164 ; GFX9: %[[SHR:[0-9]+]]:vgpr_32 = V_LSHRREV_B32_e64 16, %0
166 ; GFX9: V_AND_OR_B32_e64 %1, killed %[[IMM]], killed %[[SHR]]
/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/
H A Darm64-bitfield-extract.ll158 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
186 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
218 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
251 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
284 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
390 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
422 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
457 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
489 ; OPT-NEXT: [[AND1:%.*]] = and i64 [[SHR]], 7
618 ; OPT-NEXT: [[AND1:%.*]] = and i32 [[SHR]], 7
[all …]
/llvm-project-15.0.7/llvm/test/Transforms/AggressiveInstCombine/
H A Drotate.ll211 ; CHECK-NEXT: [[SHR:%.*]] = lshr i12 [[A]], [[B]]
212 ; CHECK-NEXT: [[OR:%.*]] = or i12 [[SHL]], [[SHR]]
244 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A]], [[B]]
245 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
277 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A]], [[B]]
278 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
317 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A]], [[B]]
318 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
350 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 [[A]], [[B]]
412 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[A]], [[B]]
[all …]
H A Dfunnel.ll216 ; CHECK-NEXT: [[SHR:%.*]] = lshr i12 [[B:%.*]], [[C]]
217 ; CHECK-NEXT: [[OR:%.*]] = or i12 [[SHL]], [[SHR]]
249 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
250 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
282 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
283 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
322 ; CHECK-NEXT: [[SHR:%.*]] = lshr i32 [[B:%.*]], [[C]]
323 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
356 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
418 ; CHECK-NEXT: [[OR:%.*]] = or i32 [[SHL]], [[SHR]]
[all …]
H A Dpr50555.ll7 ; CHECK-NEXT: [[SHR:%.*]] = lshr i16 [[ZEXT]], 1
8 ; CHECK-NEXT: [[ADD:%.*]] = add i16 [[ZEXT]], [[SHR]]
/llvm-project-15.0.7/llvm/test/MC/X86/
H A Dintel-syntax-bitwise-ops.s44 add eax, 9876 SHR 1
58 add eax, 6 XOR 3 shl 1 SHR 1
/llvm-project-15.0.7/llvm/test/Transforms/InstSimplify/
H A Dshift-128-kb.ll15 ; CHECK-NEXT: [[SHR:%.*]] = ashr i128 [[SHL]], [[SH_PROM]]
16 ; CHECK-NEXT: [[CMP:%.*]] = icmp slt i128 [[SHR]], 0
/llvm-project-15.0.7/llvm/test/Transforms/IndVarSimplify/
H A Dpr32045.ll9 ; CHECK-NEXT: [[SHR:%.*]] = ashr i32 %neg3, -1
10 ; CHECK-NEXT: [[SUB:%.*]] = sub nsw i32 0, [[SHR]]
/llvm-project-15.0.7/mlir/test/Dialect/Math/
H A Dexpand-math.mlir35 // CHECK: %[[SHR:.+]] = arith.shrui %[[A1]], %[[C1]]
37 // CHECK: scf.yield %[[SHR]], %[[SUB]], %[[A3]]
/llvm-project-15.0.7/llvm/test/tools/llvm-ml/
H A Dnamed_operators.asm85 t12 BYTE 6 SHR 2
86 BYTE 16 SHR 3
87 BYTE 7 SHR 1
/llvm-project-15.0.7/llvm/test/Transforms/InstCombine/AArch64/
H A Dsve-intrinsic-abs-srshl.ll84 ; CHECK-NEXT: [[SHR:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale…
85 ; CHECK-NEXT: ret <vscale x 8 x i16> [[SHR]]
97 ; CHECK-NEXT: [[SHR:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale…
98 ; CHECK-NEXT: ret <vscale x 8 x i16> [[SHR]]
110 ; CHECK-NEXT: [[SHR:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale…
111 ; CHECK-NEXT: ret <vscale x 8 x i16> [[SHR]]
123 ; CHECK-NEXT: [[SHR:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale…
124 ; CHECK-NEXT: ret <vscale x 8 x i16> [[SHR]]
135 ; CHECK-NEXT: [[SHR:%.*]] = tail call <vscale x 8 x i16> @llvm.aarch64.sve.srshl.nxv8i16(<vscale…
136 ; CHECK-NEXT: ret <vscale x 8 x i16> [[SHR]]
/llvm-project-15.0.7/llvm/test/Transforms/GVN/
H A Dpr33549.ll14 ; CHECK-NEXT: [[SHR:%.*]] = ashr exact i32 [[SHL]], 1
18 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 [[SHR]], 2
22 ; CHECK-NEXT: [[ADD:%.*]] = add nsw i32 [[I_030]], [[SHR]]
/llvm-project-15.0.7/llvm/test/Transforms/SLPVectorizer/X86/
H A Dpr18060.ll24 ; CHECK-NEXT: [[SHR:%.*]] = lshr i64 [[VALUE]], 16
25 ; CHECK-NEXT: [[EXTRACT_T5:%.*]] = trunc i64 [[SHR]] to i32

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