Home
last modified time | relevance | path

Searched refs:OutputArg (Results 1 – 25 of 66) sorted by relevance

123

/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsCCState.h52 void PreAnalyzeReturnForF128(const SmallVectorImpl<ISD::OutputArg> &Outs);
57 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
74 PreAnalyzeReturnForVectorFloat(const SmallVectorImpl<ISD::OutputArg> &Outs);
104 const SmallVectorImpl<ISD::OutputArg> &Outs, CCAssignFn Fn, in PreAnalyzeCallOperands()
114 AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
125 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
168 void PreAnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeReturn()
177 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
183 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags, in CheckReturn()
H A DMipsCCState.cpp99 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForF128()
121 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeReturnForVectorFloat()
123 ISD::OutputArg Out = Outs[i]; in PreAnalyzeReturnForVectorFloat()
144 const SmallVectorImpl<ISD::OutputArg> &Outs, in PreAnalyzeCallOperands()
/llvm-project-15.0.7/llvm/lib/Target/LoongArch/
H A DLoongArchISelLowering.h77 const SmallVectorImpl<ISD::OutputArg> &Outs,
80 const SmallVectorImpl<ISD::OutputArg> &Outs,
96 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/Sparc/
H A DSparcISelLowering.h149 const SmallVectorImpl<ISD::OutputArg> &Outs,
153 const SmallVectorImpl<ISD::OutputArg> &Outs,
158 const SmallVectorImpl<ISD::OutputArg> &Outs,
163 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/include/llvm/CodeGen/
H A DTargetCallingConv.h233 struct OutputArg { struct
249 OutputArg() = default; argument
250 OutputArg(ArgFlagsTy flags, MVT vt, EVT argvt, bool isfixed, in OutputArg() function
H A DCallingConvLower.h292 void AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
298 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
303 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs,
313 void AnalyzeArguments(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeArguments()
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCCCState.h23 PreAnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs);
57 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
H A DPPCCCState.cpp17 const SmallVectorImpl<ISD::OutputArg> &Outs) { in PreAnalyzeCallOperands()
H A DPPCISelLowering.h1240 bool isVarArg, const SmallVectorImpl<ISD::OutputArg> &Outs,
1343 const SmallVectorImpl<ISD::OutputArg> &Outs,
1347 const SmallVectorImpl<ISD::OutputArg> &Outs,
1374 const SmallVectorImpl<ISD::OutputArg> &Outs,
1381 const SmallVectorImpl<ISD::OutputArg> &Outs,
1388 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/Lanai/
H A DLanaiISelLowering.h95 const SmallVectorImpl<ISD::OutputArg> &Outs,
121 const SmallVectorImpl<ISD::OutputArg> &Outs,
149 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h144 const SmallVectorImpl<ISD::OutputArg> &Outs,
174 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/ARC/
H A DARCISelLowering.h108 const SmallVectorImpl<ISD::OutputArg> &Outs,
114 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
/llvm-project-15.0.7/llvm/lib/Target/XCore/
H A DXCoreISelLowering.h154 const SmallVectorImpl<ISD::OutputArg> &Outs,
221 const SmallVectorImpl<ISD::OutputArg> &Outs,
228 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DCallingConvLower.cpp96 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in CheckReturn()
110 void CCState::AnalyzeReturn(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeReturn()
123 void CCState::AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()
/llvm-project-15.0.7/llvm/lib/Target/CSKY/
H A DCSKYISelLowering.h63 const SmallVectorImpl<ISD::OutputArg> &Outs,
67 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/AVR/
H A DAVRISelLowering.h164 const SmallVectorImpl<ISD::OutputArg> &Outs,
168 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DWebAssemblyISelLowering.h97 const SmallVectorImpl<ISD::OutputArg> &Outs,
100 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/M68k/
H A DM68kISelLowering.h246 const SmallVectorImpl<ISD::OutputArg> &Outs,
273 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/VE/
H A DVEISelLowering.h98 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
101 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVISelLowering.h514 const SmallVectorImpl<ISD::OutputArg> &Outs,
517 const SmallVectorImpl<ISD::OutputArg> &Outs,
619 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/NVPTX/
H A DNVPTXISelLowering.h503 const SmallVectorImpl<ISD::OutputArg> &,
508 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/BPF/
H A DBPFISelLowering.h101 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/Hexagon/
H A DHexagonISelLowering.h121 bool isCallerStructRet, const SmallVectorImpl<ISD::OutputArg> &Outs,
225 const SmallVectorImpl<ISD::OutputArg> &Outs,
229 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/AMDGPU/
H A DSIISelLowering.h346 const SmallVectorImpl<ISD::OutputArg> &Outs,
350 const SmallVectorImpl<ISD::OutputArg> &Outs,
373 const SmallVectorImpl<ISD::OutputArg> &Outs,
/llvm-project-15.0.7/llvm/lib/Target/SystemZ/
H A DSystemZCallingConv.h65 void AnalyzeCallOperands(const SmallVectorImpl<ISD::OutputArg> &Outs, in AnalyzeCallOperands()

123