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Searched refs:MachineScheduler (Results 1 – 19 of 19) sorted by relevance

/llvm-project-15.0.7/llvm/lib/CodeGen/
H A DMachineScheduler.cpp179 class MachineScheduler : public MachineSchedulerBase { class
181 MachineScheduler();
210 char MachineScheduler::ID = 0;
212 char &llvm::MachineSchedulerID = MachineScheduler::ID;
214 INITIALIZE_PASS_BEGIN(MachineScheduler, DEBUG_TYPE,
221 INITIALIZE_PASS_END(MachineScheduler, DEBUG_TYPE, in INITIALIZE_PASS_DEPENDENCY()
224 MachineScheduler::MachineScheduler() : MachineSchedulerBase(ID) { in INITIALIZE_PASS_DEPENDENCY()
228 void MachineScheduler::getAnalysisUsage(AnalysisUsage &AU) const { in getAnalysisUsage()
337 ScheduleDAGInstrs *MachineScheduler::createMachineScheduler() { in createMachineScheduler()
381 bool MachineScheduler::runOnMachineFunction(MachineFunction &mf) { in runOnMachineFunction()
H A DRegAllocBasic.cpp136 INITIALIZE_PASS_DEPENDENCY(MachineScheduler) in INITIALIZE_PASS_DEPENDENCY()
H A DCMakeLists.txt132 MachineScheduler.cpp
H A DRegAllocGreedy.cpp156 INITIALIZE_PASS_DEPENDENCY(MachineScheduler)
/llvm-project-15.0.7/llvm/test/CodeGen/X86/
H A Dmisched-new.ll9 ; Interesting MachineScheduler cases.
H A Dmisched-matmul.ll4 ; Verify that register pressure heuristics are working in MachineScheduler.
/llvm-project-15.0.7/llvm/utils/gn/secondary/llvm/lib/CodeGen/
H A DBUILD.gn141 "MachineScheduler.cpp",
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dlower-lds-struct-aa.ll11 ; are not adjacent. They are only moved later by MachineScheduler.
/llvm-project-15.0.7/llvm/lib/Target/RISCV/
H A DRISCVSchedRocket.td11 // This works with MachineScheduler. See MCSchedule.h for details.
/llvm-project-15.0.7/llvm/lib/Target/WebAssembly/
H A DREADME.txt141 coloring. Consider experimenting with the MachineScheduler (enable via
/llvm-project-15.0.7/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX.td17 // This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
H A DAArch64SchedA53.td15 // This works with MachineScheduler. See MCSchedule.h for details.
H A DAArch64SchedA55.td18 // This works with MachineScheduler. See MCSchedModel.h for details.
H A DAArch64SchedTSV110.td16 // This works with MachineScheduler. See llvm/MC/MCSchedule.h for details.
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARM.td493 // Use the MachineScheduler for instruction scheduling for the subtarget.
495 "Use the MachineScheduler">;
H A DARMScheduleR52.td19 // This scheduler is a MachineScheduler. See TargetSchedule.td for details.
H A DARMScheduleSwift.td15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
H A DARMScheduleA9.td15 // required until SD and PostRA schedulers are replaced by MachineScheduler.
1879 // This works with MachineScheduler and will eventually replace itineraries.
/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86ScheduleZnver3.td38 // FIXME: PR50584: MachineScheduler/PostRAScheduler have quadradic complexity,