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Searched refs:LSLS (Results 1 – 4 of 4) sorted by relevance

/llvm-project-15.0.7/llvm/test/MC/ARM/
H A Dthumb2-narrow-dp.ll280 LSLS r0, r2, r1 // Must be wide - 3 distinct registers
281 LSLS r2, r2, r1 // Should choose narrow
282 LSLS r2, r1, r2 // Should choose wide - not commutative
283 LSLS.W r0, r0, r1 // Explicitly wide
284 LSLS.W r4, r1, r4
286 LSLS r7, r7, r1 // Should use narrow
287 LSLS r8, r1, r8 // high registers so must use wide encoding
288 LSLS r8, r8, r1
289 LSLS r3, r8, r3
290 LSLS r5, r5, r8
/llvm-project-15.0.7/llvm/lib/Target/ARM/
H A DARMISelLowering.h112 LSLS, // Shift left producing carry enumerator
H A DARMInstrInfo.td202 def ARMlsls : SDNode<"ARMISD::LSLS", SDTBinaryArithWithFlags>;
H A DARMISelLowering.cpp1709 MAKE_CASE(ARMISD::LSLS) in getTargetNodeName()
4786 SDValue Shift = DAG.getNode(ARMISD::LSLS, dl, in getARMCmp()