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Searched refs:In64BitMode (Results 1 – 24 of 24) sorted by relevance

/llvm-project-15.0.7/llvm/lib/Target/X86/
H A DX86InstrSNP.td21 Requires<[In64BitMode]>;
26 XD, Requires<[In64BitMode]>;
35 Requires<[In64BitMode]>;
40 Requires<[In64BitMode]>;
43 def : InstAlias<"psmash\t{%rax|rax}", (PSMASH)>, Requires<[In64BitMode]>;
44 def : InstAlias<"pvalidate\t{%rax|rax}", (PVALIDATE64)>, Requires<[In64BitMode]>;
46 def : InstAlias<"rmpupdate\t{%rax|rax}", (RMPUPDATE)>, Requires<[In64BitMode]>;
47 def : InstAlias<"rmpadjust\t{%rax|rax}", (RMPADJUST)>, Requires<[In64BitMode]>;
H A DX86InstrSVM.td37 Requires<[In64BitMode]>;
45 Requires<[In64BitMode]>;
53 Requires<[In64BitMode]>;
61 "invlpga", []>, TB, Requires<[In64BitMode]>;
66 def : InstAlias<"vmrun\t{%rax|rax}", (VMRUN64), 0>, Requires<[In64BitMode]>;
68 def : InstAlias<"vmload\t{%rax|rax}", (VMLOAD64), 0>, Requires<[In64BitMode]>;
70 def : InstAlias<"vmsave\t{%rax|rax}", (VMSAVE64), 0>, Requires<[In64BitMode]>;
72 def : InstAlias<"invlpga\t{%rax, %ecx|rax, ecx}", (INVLPGA64), 0>, Requires<[In64BitMode]>;
H A DX86InstrVMX.td24 Requires<[In64BitMode]>;
32 Requires<[In64BitMode]>;
52 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
60 "vmread{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
68 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
76 "vmwrite{q}\t{$src, $dst|$dst, $src}", []>, PS, Requires<[In64BitMode]>,
H A DX86InstrControl.td26 "ret{q}", []>, OpSize32, Requires<[In64BitMode]>;
38 "{l}ret{|f}q", []>, Requires<[In64BitMode]>;
44 "{l}ret{|f}q\t$amt", []>, Requires<[In64BitMode]>;
142 [(brind GR64:$dst)]>, Requires<[In64BitMode]>,
338 Requires<[In64BitMode]>;
344 Requires<[In64BitMode,FavorMemIndirectCall,
351 Requires<[In64BitMode]>, NOTRACK;
407 Requires<[In64BitMode,UseIndirectThunkCalls]>;
423 Requires<[In64BitMode]>;
427 Requires<[In64BitMode]>;
[all …]
H A DX86InstrSystem.td64 Requires<[In64BitMode]>;
70 Requires<[In64BitMode]>;
131 Requires<[In64BitMode]>;
138 Requires<[In64BitMode]>;
150 Requires<[In64BitMode]>;
157 Requires<[In64BitMode]>;
180 Requires<[In64BitMode]>;
322 OpSize32, Requires<[In64BitMode]>;
329 OpSize32, Requires<[In64BitMode]>;
660 let Predicates = [In64BitMode, HasINVPCID] in {
[all …]
H A DX86InstrExtension.td22 "{cltq|cdqe}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
34 "{cqto|cqo}", []>, Sched<[WriteALU]>, Requires<[In64BitMode]>;
158 Sched<[WriteALU]>, Requires<[In64BitMode]>;
162 Sched<[WriteALULd]>, Requires<[In64BitMode]>;
170 Sched<[WriteALU]>, OpSize16, Requires<[In64BitMode]>;
173 Sched<[WriteALU]>, OpSize32, Requires<[In64BitMode]>;
177 Sched<[WriteALULd]>, OpSize16, Requires<[In64BitMode]>;
180 Sched<[WriteALULd]>, OpSize32, Requires<[In64BitMode]>;
H A DX86InstrInfo.td1281 Requires<[In64BitMode]>;
1382 Requires<[In64BitMode]>;
1395 Requires<[In64BitMode]>;
1552 Requires<[In64BitMode]>;
1567 Requires<[In64BitMode]>;
1581 Requires<[In64BitMode]>;
1592 Requires<[In64BitMode]>;
1945 Requires<[In64BitMode]>;
2278 Requires<[In64BitMode]>;
2826 Requires<[ In64BitMode ]>;
[all …]
H A DX86InstrShiftRotate.td83 Requires<[In64BitMode]>;
101 Requires<[In64BitMode]>;
118 Requires<[In64BitMode]>;
183 Requires<[In64BitMode]>;
201 Requires<[In64BitMode]>;
218 Requires<[In64BitMode]>;
286 Requires<[In64BitMode]>;
304 Requires<[In64BitMode]>;
321 Requires<[In64BitMode]>;
535 Requires<[In64BitMode]>;
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H A DX86InstrTDX.td18 let SchedRW = [WriteSystem], Predicates = [In64BitMode] in {
H A DX86InstrAMX.td17 let Predicates = [HasAMXTILE, In64BitMode] in {
88 let Predicates = [HasAMXINT8, In64BitMode] in {
160 let Predicates = [HasAMXBF16, In64BitMode] in {
H A DX86InstrCompiler.td118 Requires<[In64BitMode]>;
135 Requires<[In64BitMode]>;
161 Requires<[In64BitMode]>;
216 Requires<[In64BitMode]>;
225 Requires<[In64BitMode]>;
486 Requires<[In64BitMode, IsLP64]>;
524 Requires<[In64BitMode]>;
1709 Requires<[In64BitMode]>;
1712 Requires<[In64BitMode]>;
1777 Requires<[In64BitMode]>;
[all …]
H A DX86InstrArithmetic.td105 Requires<[In64BitMode]>;
143 Requires<[In64BitMode]>;
311 Requires<[In64BitMode]>;
342 Requires<[In64BitMode]>;
998 let Predicates = [In64BitMode] in
1004 let Predicates = [In64BitMode] in
1083 let Predicates = [In64BitMode] in
1089 let Predicates = [In64BitMode] in
1164 let Predicates = [In64BitMode] in
1170 let Predicates = [In64BitMode] in
[all …]
H A DX86InstrFPStack.td768 PS, Requires<[HasFXSR, In64BitMode]>;
777 PS, Requires<[HasFXSR, In64BitMode]>;
H A DX86InstrMMX.td558 let Uses = [RDI], Predicates = [HasMMX, HasSSE1,In64BitMode] in
H A DX86InstrFormats.td1011 : I<o, F, outs, ins, asm, pattern>, PS, Requires<[HasMMX,In64BitMode]>;
H A DX86InstrSSE.td4069 let Uses = [RDI], Predicates = [HasAVX,In64BitMode] in
4080 let Uses = [RDI], Predicates = [UseSSE2,In64BitMode] in
4964 TB, Requires<[HasSSE3, In64BitMode]>;
4972 def : InstAlias<"mwait\t{%rax, %rcx|rcx, rax}", (MWAITrr)>, Requires<[In64BitMode]>;
4977 Requires<[In64BitMode]>;
H A DX86ISelLowering.cpp6265 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64); in getConstVector() local
6266 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) { in getConstVector()
6296 bool In64BitMode = DAG.getTargetLoweringInfo().isTypeLegal(MVT::i64); in getConstVector() local
6297 if (!In64BitMode && VT.getVectorElementType() == MVT::i64) { in getConstVector()
H A DX86InstrAVX512.td4032 Requires<[HasAVX512, In64BitMode]>;
/llvm-project-15.0.7/llvm/lib/Target/PowerPC/
H A DPPCInstr64Bit.td84 Requires<[In64BitMode]>;
88 Requires<[In64BitMode]>;
92 Requires<[In64BitMode]>;
95 Requires<[In64BitMode]>;
169 Requires<[In64BitMode]>;
173 Requires<[In64BitMode]>;
176 Requires<[In64BitMode]>;
221 Requires<[In64BitMode]>;
231 Requires<[In64BitMode]>;
479 Requires<[In64BitMode]>;
[all …]
H A DPPCInstrVSX.td1294 Requires<[In64BitMode]>;
1300 Requires<[In64BitMode]>;
1312 Requires<[In64BitMode]>;
1318 Requires<[In64BitMode]>;
1345 []>, Requires<[In64BitMode]>;
1349 []>, Requires<[In64BitMode]>;
H A DPPCInstrInfo.td677 def In64BitMode : Predicate<"Subtarget->isPPC64()">;
4968 let Predicates = [In64BitMode] in
/llvm-project-15.0.7/llvm/lib/Target/Mips/
H A DMipsInstrFPU.td105 // S64 - single precision in 32 64bit fp registers (In64BitMode)
107 // D64 - double precision in 32 64bit fp registers (In64BitMode)
/llvm-project-15.0.7/llvm/include/llvm/Target/
H A DTarget.td1537 /// def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;
1542 /// def : MnemonicAlias<"pushf", "pushfq", "att">, Requires<[In64BitMode]>;
/llvm-project-15.0.7/llvm/docs/
H A DCodeGenerator.rst1762 def : MnemonicAlias<"pushf", "pushfq">, Requires<[In64BitMode]>;