Searched refs:DefRegs (Results 1 – 10 of 10) sorted by relevance
| /llvm-project-15.0.7/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 107 SmallVector<MCRegister, 4> DefRegs; member
148 RegsToInvalidate.insert(I->second.DefRegs.begin(), in invalidateRegister()
149 I->second.DefRegs.end()); in invalidateRegister()
165 markRegsUnavailable(I->second.DefRegs, TRI); in clobberRegister()
198 if (!is_contained(Copy.DefRegs, Def)) in trackCopy()
199 Copy.DefRegs.push_back(Def); in trackCopy()
223 if (CI->second.DefRegs.size() != 1) in findCopyDefViaUnit()
225 MCRegUnitIterator RUI(CI->second.DefRegs[0], &TRI); in findCopyDefViaUnit()
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| H A D | MachineOutliner.cpp | 805 SmallSet<Register, 2> UseRegs, DefRegs; in outline() local
825 DefRegs.insert(MOP.getReg()); in outline()
842 for (const Register &I : DefRegs) in outline()
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| H A D | LiveVariables.cpp | 509 SmallVector<unsigned, 4> DefRegs; in runOnInstr() local
531 DefRegs.push_back(MOReg); in runOnInstr()
549 for (unsigned MOReg : DefRegs) { in runOnInstr()
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| /llvm-project-15.0.7/llvm/lib/Target/AMDGPU/ |
| H A D | AMDGPURegisterBankInfo.cpp | 2205 if (DefRegs.empty()) in applyMappingImpl()
2206 DefRegs.push_back(DstReg); in applyMappingImpl()
2207 B.buildTrunc(DefRegs[0], NewDstReg); in applyMappingImpl()
2243 if (DefRegs.empty()) { in applyMappingImpl()
2259 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
2321 if (DefRegs.empty()) { in applyMappingImpl()
2326 assert(DefRegs.size() == 2); in applyMappingImpl()
2345 setRegsToType(MRI, DefRegs, HalfTy); in applyMappingImpl()
2561 B.buildSExtOrTrunc(DefRegs[0], SrcReg); in applyMappingImpl()
2568 extendLow32IntoHigh32(B, DefRegs[1], DefRegs[0], Opc, *SrcBank); in applyMappingImpl()
[all …]
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| /llvm-project-15.0.7/llvm/lib/Target/Hexagon/ |
| H A D | HexagonExpandCondsets.cpp | 470 std::set<RegisterRef> DefRegs; in updateDeadsInRange() local
480 DefRegs.insert(Op); in updateDeadsInRange()
500 if (!Op.isReg() || !DefRegs.count(Op)) in updateDeadsInRange()
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| H A D | HexagonConstPropagation.cpp | 2842 SmallVector<unsigned,2> DefRegs; in rewriteHexConstDefs() local
2851 DefRegs.push_back(R); in rewriteHexConstDefs()
2864 for (unsigned i = 0, n = DefRegs.size(); i < n; ++i) { in rewriteHexConstDefs()
2865 unsigned R = DefRegs[i]; in rewriteHexConstDefs()
2956 AllDefs = (ChangedNum == DefRegs.size()); in rewriteHexConstDefs()
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| /llvm-project-15.0.7/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.td | 1680 list<Register> DefRegs> :
1684 let Defs = DefRegs;
1716 list<Register> DefRegs> :
1719 let Defs = DefRegs;
1740 class MoveToLOHI<string opstr, RegisterOperand RO, list<Register> DefRegs>:
1743 let Defs = DefRegs;
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| /llvm-project-15.0.7/llvm/lib/Target/VE/ |
| H A D | VEISelLowering.cpp | 2640 DenseMap<Register, bool> DefRegs; in emitSjLjDispatchBlock() local
2643 DefRegs[MOp.getReg()] = true; in emitSjLjDispatchBlock()
2648 if (!DefRegs[Reg]) in emitSjLjDispatchBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/ARM/ |
| H A D | ARMISelLowering.cpp | 11057 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
11062 DefRegs[OI->getReg()] = true; in EmitSjLjDispatchBlock()
11077 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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| /llvm-project-15.0.7/llvm/lib/Target/X86/ |
| H A D | X86ISelLowering.cpp | 36219 DenseMap<unsigned, bool> DefRegs; in EmitSjLjDispatchBlock() local
36222 DefRegs[MOp.getReg()] = true; in EmitSjLjDispatchBlock()
36227 if (!DefRegs[Reg]) in EmitSjLjDispatchBlock()
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