Home
last modified time | relevance | path

Searched refs:DEF (Results 1 – 25 of 350) sorted by relevance

12345678910>>...14

/llvm-project-15.0.7/llvm/test/CodeGen/AArch64/GlobalISel/
H A Dlegalize-min-max.mir56 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
57 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
58 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
59 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
339 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
340 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
341 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
342 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
643 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
644 …DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s8), [[DEF]](s…
[all …]
H A Dlegalize-build-vector.mir64 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
66 …DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1…
80 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
82 …]]:_(<8 x s8>) = G_BUILD_VECTOR [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8),…
96 ; CHECK: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF
98 …DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1]](s8), [[DEF]](s8), [[DEF1…
H A Dlegalize-fp-arith.mir81 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
82 ; CHECK: [[FMUL:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[DEF]], [[DEF]]
83 ; CHECK: [[FMUL1:%[0-9]+]]:_(<2 x s64>) = G_FMUL [[DEF]], [[DEF]]
99 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
100 …UILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
101 …ILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
102 …ILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
103 …ILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[DEF]](s32), [[DEF]](s32), [[DEF]](s32), [[DE…
H A Dlegalize-undef.mir10 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
11 ; CHECK: $x0 = COPY [[DEF]](s64)
24 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
40 ; CHECK: [[DEF:%[0-9]+]]:_(<4 x s32>) = G_IMPLICIT_DEF
56 ; CHECK: [[DEF:%[0-9]+]]:_(<2 x s64>) = G_IMPLICIT_DEF
57 ; CHECK: $q0 = COPY [[DEF]](<2 x s64>)
58 ; CHECK: $q1 = COPY [[DEF]](<2 x s64>)
86 ; CHECK: $q0 = COPY [[DEF]](<16 x s8>)
97 ; CHECK: $q0 = COPY [[DEF]](<8 x s16>)
107 ; CHECK: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
[all …]
H A Drbs-matrixindex-regclass-crash.mir14 ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
15 ; CHECK-NEXT: $x1 = COPY [[DEF]](s64)
16 ; CHECK-NEXT: $x2 = COPY [[DEF]](s64)
17 ; CHECK-NEXT: $x3 = COPY [[DEF]](s64)
18 ; CHECK-NEXT: $x4 = COPY [[DEF]](s64)
19 ; CHECK-NEXT: $x5 = COPY [[DEF]](s64)
20 ; CHECK-NEXT: $x6 = COPY [[DEF]](s64)
21 ; CHECK-NEXT: $x7 = COPY [[DEF]](s64)
22 ; CHECK-NEXT: $x8 = COPY [[DEF]](s64)
23 ; CHECK-NEXT: $x9 = COPY [[DEF]](s64)
[all …]
H A Dlegalize-cmp.mir47 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
88 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
90 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
91 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
123 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
126 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
164 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
167 ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[DEF]], [[C]]
205 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
245 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s64) = G_IMPLICIT_DEF
[all …]
H A Dlegalize-xor.mir35 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
36 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
37 ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
38 ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
39 ; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
79 ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
80 ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
81 ; CHECK-NEXT: [[XOR2:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
82 ; CHECK-NEXT: [[XOR3:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
83 ; CHECK-NEXT: [[XOR4:%[0-9]+]]:_(s64) = G_XOR [[DEF]], [[DEF]]
[all …]
H A Dprelegalizercombiner-undef.mir93 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
94 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
111 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
128 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
145 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
161 ; CHECK-NEXT: $w0 = COPY [[DEF]](s32)
177 ; CHECK-NEXT: $d0 = COPY [[DEF]](<2 x s32>)
197 ; CHECK-NEXT: $d0 = COPY [[DEF]](<2 x s32>)
239 ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
256 ; CHECK-NEXT: $x0 = COPY [[DEF]](s64)
[all …]
/llvm-project-15.0.7/mlir/test/mlir-tblgen/
H A Dop-attribute.td73 // DEF-NEXT: while (true) {
78 // DEF-NEXT: break;
81 // DEF-NEXT: while (true) {
83 // DEF-NEXT: break;
108 // DEF-NEXT: if (!attr)
140 // DEF: if (cAttr) {
198 // DEF-NEXT: while (true)
201 // DEF-NEXT: while (true)
222 // DEF-NEXT: if (!attr)
385 // DEF: return false;
[all …]
H A Dattrdefs.td15 // DEF: #ifdef GET_ATTRDEF_LIST
16 // DEF: #undef GET_ATTRDEF_LIST
17 // DEF: ::test::SimpleAAttr,
18 // DEF: ::test::CompoundAAttr,
19 // DEF: ::test::IndexAttr,
30 // DEF-NEXT: })
40 // DEF-NOT: TestDialect
83 // DEF: CompoundAAttrStorage(
87 // DEF-NEXT: return
179 // DEF: return i+1;
[all …]
H A Ddialect.td48 // DEF-LABEL: GET_OP_LIST
49 // DEF: a::SomeOp
50 // DEF-NEXT: BNS::SomeOp
51 // DEF-NEXT: ::C::CC::SomeOp
52 // DEF-NEXT: DSomeOp
53 // DEF-NEXT: ENS::SomeOp
56 // DEF-LABEL: GET_OP_CLASSES
57 // DEF: a::SomeOp definitions
58 // DEF: BNS::SomeOp definitions
60 // DEF: DSomeOp definitions
[all …]
H A Dtypedefs.td15 // DEF: #ifdef GET_TYPEDEF_LIST
16 // DEF: #undef GET_TYPEDEF_LIST
17 // DEF: ::test::SimpleAType,
18 // DEF: ::test::CompoundAType,
19 // DEF: ::test::IndexType,
20 // DEF: ::test::SingleParameterType,
21 // DEF: ::test::IntegerType
26 // DEF-SAME: ::mlir::Type &value) {
30 // DEF-NEXT: })
35 // DEF-NEXT: *mnemonic = keyword;
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/GlobalISel/
H A Dinst-select-extract.mir11 ; CHECK: [[DEF:%[0-9]+]]:sgpr_512 = IMPLICIT_DEF
12 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
13 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
14 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub2
15 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub3
16 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub4
17 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub5
18 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub6
19 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub7
89 ; CHECK: [[DEF:%[0-9]+]]:sgpr_1024 = IMPLICIT_DEF
[all …]
H A Dinst-select-implicit-def.mir13 ; GCN: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
14 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
27 ; GCN: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
28 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
43 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
58 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
72 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
86 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
153 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
168 ; GCN-NEXT: S_ENDPGM 0, implicit [[DEF]]
[all …]
H A Dlegalize-implicit-def.mir11 ; CHECK: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
12 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
25 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
38 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
51 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
64 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](s32)
352 …0-9]+]]:_(<64 x s32>) = G_CONCAT_VECTORS [[DEF]](<16 x s32>), [[DEF]](<16 x s32>), [[DEF]](<16 x s…
353 … [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[DEF]](<16 x s32>), [[DEF]](<16 x s…
638 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](p2)
650 ; CHECK-NEXT: $vgpr0 = COPY [[DEF]](p3)
[all …]
H A Dlegalize-anyext.mir302 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
323 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
343 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
364 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
384 ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s32) = G_IMPLICIT_DEF
505 ; CHECK-NEXT: [[MV:%[0-9]+]]:_(s192) = G_MERGE_VALUES [[COPY]](s64), [[DEF]](s64), [[DEF]](s64)
523 …XT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[COPY]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64)
541 … G_MERGE_VALUES [[COPY]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64…
559 …DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[DEF]](s64), [[…
599 …NEXT: [[MV:%[0-9]+]]:_(s256) = G_MERGE_VALUES [[UV]](s64), [[UV1]](s64), [[DEF]](s64), [[DEF]](s64)
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/AMDGPU/
H A Dsi-fold-aligned-vgprs.mir17 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
23 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
41 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
47 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:vreg_64 = IMPLICIT_DEF
66 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
72 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
90 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_96_align2 = IMPLICIT_DEF
139 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_96 = IMPLICIT_DEF
145 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:vreg_96 = IMPLICIT_DEF
310 ; GFX908-NEXT: [[DEF:%[0-9]+]]:vreg_128 = IMPLICIT_DEF
[all …]
H A Dgfx10-shrink-mad-fma.mir9 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
24 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
39 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
54 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
69 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
84 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
99 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
114 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
129 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
144 ; GFX10: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
[all …]
H A Dsi-fold-aligned-agprs.mir16 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_64_align2 = IMPLICIT_DEF
34 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_64 = IMPLICIT_DEF
53 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_96_align2 = IMPLICIT_DEF
71 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_96_align2 = IMPLICIT_DEF
90 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_96_align2 = IMPLICIT_DEF
108 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_96 = IMPLICIT_DEF
127 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_128_align2 = IMPLICIT_DEF
145 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_128_align2 = IMPLICIT_DEF
163 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_128_align2 = IMPLICIT_DEF
182 ; GFX90A-NEXT: [[DEF:%[0-9]+]]:areg_128_align2 = IMPLICIT_DEF
[all …]
H A Dmerge-flat-load-store.mir10 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
27 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
47 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
70 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
95 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
123 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
140 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
157 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
174 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
190 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
[all …]
H A Dmerge-global-load-store.mir10 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
27 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
47 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
70 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
95 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
123 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
140 ; GCN: [[DEF:%[0-9]+]]:vreg_64_align2 = IMPLICIT_DEF
238 ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
257 ; GCN: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF
371 ; GCN: [[DEF:%[0-9]+]]:sgpr_128 = IMPLICIT_DEF
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/X86/GlobalISel/
H A Dlegalize-memop-scalar-32.mir12 ; X32: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
13 ; X32: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load (s1))
14 ; X32: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load (s8))
15 ; X32: [[LOAD2:%[0-9]+]]:_(s16) = G_LOAD [[DEF]](p0) :: (load (s16))
17 ; X32: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
20 ; X32: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
21 ; X32: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
22 ; X32: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
23 ; X32: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store (s32))
24 ; X32: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store (p0))
[all …]
H A Dlegalize-memop-scalar-64.mir12 ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
13 ; X64: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load (s1))
14 ; X64: [[LOAD1:%[0-9]+]]:_(s8) = G_LOAD [[DEF]](p0) :: (load (s8))
17 ; X64: [[LOAD4:%[0-9]+]]:_(p0) = G_LOAD [[DEF]](p0) :: (load (p0))
20 ; X64: G_STORE [[AND]](s8), [[DEF]](p0) :: (store (s1))
21 ; X64: G_STORE [[LOAD1]](s8), [[DEF]](p0) :: (store (s8))
22 ; X64: G_STORE [[LOAD2]](s16), [[DEF]](p0) :: (store (s16))
23 ; X64: G_STORE [[LOAD3]](s32), [[DEF]](p0) :: (store (s32))
24 ; X64: G_STORE [[LOAD4]](p0), [[DEF]](p0) :: (store (p0))
48 ; X64: [[DEF:%[0-9]+]]:_(p0) = IMPLICIT_DEF
[all …]
H A Dlegalize-undef.mir13 ; X64: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
15 ; X64: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s1))
17 ; X64: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store (s8))
19 ; X64: G_STORE [[DEF2]](s16), [[DEF]](p0) :: (store (s16))
21 ; X64: G_STORE [[DEF3]](s32), [[DEF]](p0) :: (store (s32))
23 ; X64: G_STORE [[DEF4]](s64), [[DEF]](p0) :: (store (s64))
25 ; X32: [[DEF:%[0-9]+]]:_(p0) = G_IMPLICIT_DEF
27 ; X32: G_STORE [[C]](s8), [[DEF]](p0) :: (store (s1))
29 ; X32: G_STORE [[DEF1]](s8), [[DEF]](p0) :: (store (s8))
31 ; X32: G_STORE [[DEF2]](s16), [[DEF]](p0) :: (store (s16))
[all …]
/llvm-project-15.0.7/llvm/test/CodeGen/Thumb2/
H A Dmve-vpt-optimisations.mir12 ; CHECK-NEXT: [[DEF:%[0-9]+]]:mqpr = IMPLICIT_DEF
392 …; CHECK-NEXT: [[MVE_VORR1:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT1]], $noreg,…
401 …; CHECK-NEXT: [[MVE_VORR3:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT3]], $noreg,…
408 …; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg,…
674 …; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, u…
689 …; CHECK-NEXT: [[MVE_VORR5:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT5]], $noreg,…
702 …; CHECK-NEXT: [[MVE_VORR10:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT8]], $noreg…
719 …; CHECK-NEXT: [[MVE_VORR18:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT12]], $nore…
870 …; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VCMPs32_]], $noreg…
982 …; CHECK-NEXT: [[MVE_VORR:%[0-9]+]]:mqpr = MVE_VORR [[DEF]], [[DEF]], 1, [[MVE_VPNOT]], $noreg, u…
[all …]

12345678910>>...14