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Searched refs:xe_mmio_read32 (Results 1 – 25 of 40) sorted by relevance

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/linux-6.15/drivers/gpu/drm/xe/compat-i915-headers/
H A Dintel_uncore.h39 return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg); in intel_uncore_read()
67 upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg); in intel_uncore_read64_2x32()
70 lower = xe_mmio_read32(__compat_uncore_to_mmio(uncore), lower_reg); in intel_uncore_read64_2x32()
71 upper = xe_mmio_read32(__compat_uncore_to_mmio(uncore), upper_reg); in intel_uncore_read64_2x32()
82 xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg); in intel_uncore_posting_read()
147 return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg); in intel_uncore_read_fw()
163 return xe_mmio_read32(__compat_uncore_to_mmio(uncore), reg); in intel_uncore_read_notrace()
/linux-6.15/drivers/gpu/drm/xe/
H A Dxe_mmio.c78 mtcfg = xe_mmio_read32(mmio, XEHP_MTCFG_ADDR); in mmio_multi_tile_setup()
213 u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg) in xe_mmio_read32() function
235 old = xe_mmio_read32(mmio, reg); in xe_mmio_rmw32()
248 reg_val = xe_mmio_read32(mmio, reg); in xe_mmio_write32_and_verify()
295 oldudw = xe_mmio_read32(mmio, reg_udw); in xe_mmio_read64_2x32()
297 ldw = xe_mmio_read32(mmio, reg); in xe_mmio_read64_2x32()
298 udw = xe_mmio_read32(mmio, reg_udw); in xe_mmio_read64_2x32()
323 read = xe_mmio_read32(mmio, reg); in __xe_mmio_wait32()
349 read = xe_mmio_read32(mmio, reg); in __xe_mmio_wait32()
H A Dxe_guc_pc.c348 reg = xe_mmio_read32(&gt->mmio, MTL_MPA_FREQUENCY); in mtl_update_rpa_value()
380 reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP); in tgl_update_rpa_value()
383 reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC); in tgl_update_rpa_value()
400 reg = xe_mmio_read32(&gt->mmio, PVC_RP_STATE_CAP); in tgl_update_rpe_value()
403 reg = xe_mmio_read32(&gt->mmio, FREQ_INFO_REC); in tgl_update_rpe_value()
446 freq = xe_mmio_read32(&gt->mmio, GT_PERF_STATUS); in xe_guc_pc_get_act_freq()
459 freq = xe_mmio_read32(&gt->mmio, RPNSWREQ); in get_cur_freq()
678 reg = xe_mmio_read32(&gt->mmio, GT_CORE_STATUS); in xe_guc_pc_c_status()
701 reg = xe_mmio_read32(&gt->mmio, GT_GFX_RC6); in xe_guc_pc_rc6_residency()
715 reg = xe_mmio_read32(&gt->mmio, MTL_MEDIA_MC6); in xe_guc_pc_mc6_residency()
[all …]
H A Dxe_irq.c41 u32 val = xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
50 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
52 xe_mmio_read32(mmio, reg); in assert_iir_is_zero()
73 xe_mmio_read32(mmio, IMR(irqregs)); in unmask_and_enable()
83 xe_mmio_read32(mmio, IMR(irqregs)); in mask_and_disable()
89 xe_mmio_read32(mmio, IIR(irqregs)); in mask_and_disable()
91 xe_mmio_read32(mmio, IIR(irqregs)); in mask_and_disable()
106 return xe_mmio_read32(mmio, GFX_MSTR_IRQ); in xelp_intr_disable()
131 xe_mmio_read32(mmio, GFX_MSTR_IRQ); in xelp_intr_enable()
404 val = xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR); in dg1_intr_disable()
[all …]
H A Dxe_gt_mcr.c257 xe_mmio_read32(mmio, MIRROR_FUSE3)); in init_steering_l3bank()
259 xe_mmio_read32(mmio, XEHP_FUSE4)); in init_steering_l3bank()
270 xe_mmio_read32(mmio, MIRROR_FUSE3)); in init_steering_l3bank()
282 ~xe_mmio_read32(mmio, MIRROR_FUSE3)); in init_steering_l3bank()
292 xe_mmio_read32(&gt->mmio, MIRROR_FUSE3)); in init_steering_mslice()
415 xe_mmio_read32(&gt->mmio, MIRROR_FUSE3)); in init_steering_sqidi_psmi()
677 val = xe_mmio_read32(mmio, reg); in rw_with_mcr_steering()
723 val = xe_mmio_read32(&gt->mmio, reg); in xe_gt_mcr_unicast_read_any()
H A Dxe_gt_topology.c30 fuse_val[i] = xe_mmio_read32(&gt->mmio, va_arg(argp, struct xe_reg)); in load_dss_mask()
40 u32 reg_val = xe_mmio_read32(&gt->mmio, XELP_EU_ENABLE); in load_eu_mask()
133 u32 fuse3 = xe_mmio_read32(mmio, MIRROR_FUSE3); in load_l3_bank_mask()
150 u32 mirror_l3bank_enable = xe_mmio_read32(mmio, MIRROR_L3BANK_ENABLE); in load_l3_bank_mask()
168 u32 fuse4 = xe_mmio_read32(mmio, XEHP_FUSE4); in load_l3_bank_mask()
H A Dxe_gsc.c183 return xe_mmio_read32(&gt->mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)) & in gsc_fw_is_loaded()
332 er_status = xe_mmio_read32(&gt->mmio, GSCI_TIMER_STATUS) & GSCI_TIMER_STATUS_VALUE; in gsc_er_complete()
630 xe_mmio_read32(mmio, HECI_FWSTS1(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
631 xe_mmio_read32(mmio, HECI_FWSTS2(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
632 xe_mmio_read32(mmio, HECI_FWSTS3(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
633 xe_mmio_read32(mmio, HECI_FWSTS4(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
634 xe_mmio_read32(mmio, HECI_FWSTS5(MTL_GSC_HECI1_BASE)), in xe_gsc_print_info()
635 xe_mmio_read32(mmio, HECI_FWSTS6(MTL_GSC_HECI1_BASE))); in xe_gsc_print_info()
H A Dxe_pcode.c47 err = xe_mmio_read32(&tile->mmio, PCODE_MAILBOX) & PCODE_ERROR_MASK; in pcode_mailbox_status()
67 if ((xe_mmio_read32(mmio, PCODE_MAILBOX) & PCODE_READY) != 0) in __pcode_mailbox_rw()
80 *data0 = xe_mmio_read32(mmio, PCODE_DATA0); in __pcode_mailbox_rw()
82 *data1 = xe_mmio_read32(mmio, PCODE_DATA1); in __pcode_mailbox_rw()
H A Dxe_wopcm.c128 u32 reg_base = xe_mmio_read32(&gt->mmio, DMA_GUC_WOPCM_OFFSET); in __wopcm_regs_locked()
129 u32 reg_size = xe_mmio_read32(&gt->mmio, GUC_WOPCM_SIZE); in __wopcm_regs_locked()
174 xe_mmio_read32(&gt->mmio, DMA_GUC_WOPCM_OFFSET)); in __wopcm_init_regs()
177 xe_mmio_read32(&gt->mmio, GUC_WOPCM_SIZE)); in __wopcm_init_regs()
H A Dxe_gt_clock.c70 if (xe_mmio_read32(&gt->mmio, CTC_MODE) & CTC_SOURCE_DIVIDE_LOGIC) in check_ctc_mode()
82 c0 = xe_mmio_read32(&gt->mmio, RPM_CONFIG0); in xe_gt_clock_init()
H A Dxe_hwmon.c185 reg_val = xe_mmio_read32(mmio, rapl_limit); in xe_hwmon_power_max_read()
221 reg_val = xe_mmio_read32(mmio, rapl_limit); in xe_hwmon_power_max_write()
250 reg_val = xe_mmio_read32(mmio, reg); in xe_hwmon_power_rated_max_read()
282 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_ENERGY_STATUS, in xe_hwmon_energy_get()
310 r = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_PKG_RAPL_LIMIT, sensor_index)); in xe_hwmon_power_max_interval_show()
522 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_GT_PERF_STATUS, channel)); in xe_hwmon_get_voltage()
547 reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); in xe_hwmon_temp_read()
856 val_sku_unit = xe_mmio_read32(mmio, pkg_power_sku_unit); in xe_hwmon_get_preregistration_info()
H A Dxe_mocs.c281 reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i)); in xelp_lncf_dump()
313 reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i)); in xelp_mocs_dump()
386 reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i)); in xehp_lncf_dump()
431 reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i)); in pvc_mocs_dump()
513 reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i)); in mtl_mocs_dump()
556 reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i)); in xe2_mocs_dump()
H A Dxe_guc.c796 guc_status = xe_mmio_read32(mmio, GUC_STATUS); in xe_guc_reset()
1014 xe_mmio_read32(mmio, GUC_HEADER_INFO)); in guc_wait_ucode()
1029 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); in guc_wait_ucode()
1181 msg = xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(15)); in guc_handle_mmio_msg()
1306 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); in xe_guc_mmio_send_recv()
1311 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); in xe_guc_mmio_send_recv()
1326 header = xe_mmio_read32(mmio, reply_reg); in xe_guc_mmio_send_recv()
1389 response_buf[i] = xe_mmio_read32(mmio, reply_reg); in xe_guc_mmio_send_recv()
1515 status = xe_mmio_read32(&gt->mmio, GUC_STATUS); in xe_guc_print_info()
1530 i, xe_mmio_read32(&gt->mmio, SOFT_SCRATCH(i))); in xe_guc_print_info()
H A Dxe_hw_engine.c323 return xe_mmio_read32(&hwe->gt->mmio, reg); in xe_hw_engine_mmio_read32()
365 return xe_mmio_read32(&hwe->gt->mmio, XEHP_FUSE4) & CFEG_WMTP_DISABLE; in xe_rtp_cfeg_wmtp_disabled()
579 idledly = xe_mmio_read32(&gt->mmio, RING_IDLEDLY(hwe->mmio_base)); in adjust_idledly()
580 maxcnt = xe_mmio_read32(&gt->mmio, RING_PWRCTX_MAXCNT(hwe->mmio_base)); in adjust_idledly()
676 media_fuse = xe_mmio_read32(&gt->mmio, GT_VEBOX_VDBOX_DISABLE); in read_media_fuses()
721 bcs_mask = xe_mmio_read32(&gt->mmio, MIRROR_FUSE3); in read_copy_fuses()
768 ccs_mask = xe_mmio_read32(&gt->mmio, XEHP_FUSE4); in read_compute_fuses_from_reg()
H A Dxe_pat.c195 u32 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xelp_dump()
284 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xelpg_dump()
341 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_INDEX(i))); in xe2_dump()
360 pat = xe_mmio_read32(&gt->mmio, XE_REG(_PAT_PTA)); in xe2_dump()
H A Dxe_gt_throttle.c45 reg = xe_mmio_read32(&gt->mmio, MTL_MEDIA_PERF_LIMIT_REASONS); in xe_gt_throttle_get_limit_reasons()
47 reg = xe_mmio_read32(&gt->mmio, GT0_PERF_LIMIT_REASONS); in xe_gt_throttle_get_limit_reasons()
H A Dxe_survivability_mode.c57 info[id].value = xe_mmio_read32(mmio, PCODE_SCRATCH(id)); in set_survivability_info()
207 data = xe_mmio_read32(mmio, PCODE_SCRATCH(0)); in survivability_mode_requested()
H A Dxe_execlist.c84 xe_mmio_read32(mmio, RING_HWS_PGA(hwe->mmio_base)); in __start_lrc()
176 lo = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_LO(hwe->mmio_base)); in read_execlist_status()
177 hi = xe_mmio_read32(&gt->mmio, RING_EXECLIST_STATUS_HI(hwe->mmio_base)); in read_execlist_status()
H A Dxe_mmio.h22 u32 xe_mmio_read32(struct xe_mmio *mmio, struct xe_reg reg);
H A Dxe_huc.c232 return xe_mmio_read32(&gt->mmio, huc_auth_modes[type].reg) & huc_auth_modes[type].val; in xe_huc_is_authenticated()
311 xe_mmio_read32(&gt->mmio, HUC_KERNEL_LOAD_INFO)); in xe_huc_print_info()
H A Dxe_sriov.c41 u32 value = xe_mmio_read32(xe_root_tile_mmio(xe), VF_CAP_REG); in test_is_vf()
H A Dxe_gt_idle.c222 pg_enabled = xe_mmio_read32(&gt->mmio, POWERGATE_ENABLE); in xe_gt_idle_pg_print()
223 pg_status = xe_mmio_read32(&gt->mmio, POWERGATE_DOMAIN_STATUS); in xe_gt_idle_pg_print()
H A Dxe_reg_sr.c148 xe_mmio_read32(&gt->mmio, reg)) & (~entry->clr_bits); in apply_one_mmio()
H A Dxe_query.c99 upper = xe_mmio_read32(mmio, upper_reg); in hwe_read_timestamp()
103 lower = xe_mmio_read32(mmio, lower_reg); in hwe_read_timestamp()
106 upper = xe_mmio_read32(mmio, upper_reg); in hwe_read_timestamp()
/linux-6.15/drivers/gpu/drm/xe/tests/
H A Dxe_mocs.c60 reg_val = xe_mmio_read32(&gt->mmio, XELP_LNCFCMOCS(i >> 1)); in read_l3cc_table()
98 reg_val = xe_mmio_read32(&gt->mmio, XELP_GLOBAL_MOCS(i)); in read_mocs_table()

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