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Searched refs:wptr_offset (Results 1 – 11 of 11) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/display/dmub/
H A Ddmub_srv.h407 void (*set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
425 void (*emul_set_inbox1_wptr)(struct dmub_srv *dmub, uint32_t wptr_offset);
/linux-6.15/drivers/gpu/drm/amd/display/dmub/src/
H A Ddmub_dcn20.c296 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn20_set_inbox1_wptr() argument
298 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn20_set_inbox1_wptr()
H A Ddmub_dcn31.c261 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn31_set_inbox1_wptr() argument
263 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn31_set_inbox1_wptr()
H A Ddmub_dcn20.h210 void dmub_dcn20_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
H A Ddmub_dcn32.c285 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn32_set_inbox1_wptr() argument
287 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn32_set_inbox1_wptr()
H A Ddmub_dcn35.c307 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn35_set_inbox1_wptr() argument
309 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn35_set_inbox1_wptr()
H A Ddmub_dcn31.h212 void dmub_dcn31_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
H A Ddmub_dcn32.h219 void dmub_dcn32_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
H A Ddmub_dcn401.c281 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset) in dmub_dcn401_set_inbox1_wptr() argument
283 REG_WRITE(DMCUB_INBOX1_WPTR, wptr_offset); in dmub_dcn401_set_inbox1_wptr()
H A Ddmub_dcn35.h232 void dmub_dcn35_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);
H A Ddmub_dcn401.h229 void dmub_dcn401_set_inbox1_wptr(struct dmub_srv *dmub, uint32_t wptr_offset);