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Searched refs:top_pipe (Results 1 – 25 of 39) sorted by relevance

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/linux-6.15/drivers/gpu/drm/amd/display/dc/basics/
H A Ddc_common.c66 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_upper_pipe_tree_visible()
75 if (pipe_ctx->top_pipe && is_upper_pipe_tree_visible(pipe_ctx->top_pipe)) in is_pipe_tree_visible()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/
H A Ddml2_mall_phantom.c122 pipe->top_pipe = NULL; in merge_pipes_for_subvp()
128 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in merge_pipes_for_subvp()
129 struct pipe_ctx *top_pipe = pipe->top_pipe; in merge_pipes_for_subvp() local
132 top_pipe->bottom_pipe = bottom_pipe; in merge_pipes_for_subvp()
134 bottom_pipe->top_pipe = top_pipe; in merge_pipes_for_subvp()
136 pipe->top_pipe = NULL; in merge_pipes_for_subvp()
194 if (pipe->stream && !pipe->top_pipe) { in get_num_free_pipes()
255 if (pipe->plane_state && !pipe->top_pipe && in assign_subvp_pipe()
319 if (pipe->stream && !pipe->top_pipe && in enough_pipes_for_subvp()
616 if (pipe->plane_state && !pipe->top_pipe && in dml2_svp_validate_static_schedulability()
[all …]
H A Ddml2_dc_resource_mgmt.c115 if (!state->res_ctx.pipe_ctx[i].prev_odm_pipe && !state->res_ctx.pipe_ctx[i].top_pipe) in find_master_pipe_of_stream()
158 && (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) { in find_pipes_assigned_to_plane()
564 struct pipe_ctx *top_pipe) in add_plane_to_blend_tree() argument
569 if (top_pipe) in add_plane_to_blend_tree()
574 state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]].top_pipe = top_pipe; in add_plane_to_blend_tree()
577 top_pipe = &state->res_ctx.pipe_ctx[pipe_pool->pipes_assigned_to_plane[odm_slice][i]]; in add_plane_to_blend_tree()
582 return top_pipe; in add_plane_to_blend_tree()
726 if (pipe->top_pipe) in remove_pipes_from_blend_trees()
727 pipe->top_pipe->bottom_pipe = pipe->bottom_pipe; in remove_pipes_from_blend_trees()
730 pipe->bottom_pipe = pipe->top_pipe; in remove_pipes_from_blend_trees()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn20/
H A Ddcn20_resource.c1387 if (pipe_ctx->top_pipe) in dcn20_add_dsc_to_stream_resource()
1501 if (prev_odm_pipe->top_pipe && prev_odm_pipe->top_pipe->next_odm_pipe) { in dcn20_split_stream_for_odm()
1503 next_odm_pipe->top_pipe = prev_odm_pipe->top_pipe->next_odm_pipe; in dcn20_split_stream_for_odm()
1519 if (!next_odm_pipe->top_pipe) in dcn20_split_stream_for_odm()
1776 odm_pipe->top_pipe = NULL; in dcn20_merge_pipes_for_validate()
1804 hsplit_pipe->top_pipe = NULL; in dcn20_merge_pipes_for_validate()
1852 (!pipe->top_pipe || pipe->top_pipe->plane_state != pipe->plane_state)) in dcn20_validate_apply_pipe_split_flags()
1942 else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn20_validate_apply_pipe_split_flags()
1946 if (split[i] == 2 && ((pipe->top_pipe && !pipe->top_pipe->top_pipe) in dcn20_validate_apply_pipe_split_flags()
1984 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn20_validate_apply_pipe_split_flags()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource_helpers.c129 pipe->top_pipe = NULL; in dcn32_merge_pipes_for_subvp()
135 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn32_merge_pipes_for_subvp()
136 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn32_merge_pipes_for_subvp() local
139 top_pipe->bottom_pipe = bottom_pipe; in dcn32_merge_pipes_for_subvp()
141 bottom_pipe->top_pipe = top_pipe; in dcn32_merge_pipes_for_subvp()
143 pipe->top_pipe = NULL; in dcn32_merge_pipes_for_subvp()
/linux-6.15/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_resource.c1611 if (pipe_ctx->top_pipe && pipe_ctx->top_pipe->plane_state == plane_state) { in resource_build_scaling_params()
1960 !pipe_ctx->top_pipe && in resource_is_pipe_type()
2076 while (opp_head->top_pipe) in resource_get_opp_head()
2117 other_pipe = pipe->top_pipe; in resource_get_mpc_slice_count()
2552 if (split_pipe->top_pipe && in acquire_first_split_pipe()
2556 split_pipe->bottom_pipe->top_pipe = split_pipe->top_pipe; in acquire_first_split_pipe()
3078 if (pipe_ctx->top_pipe) in resource_remove_dpp_pipes_for_plane_composition()
3086 pipe_ctx->bottom_pipe->top_pipe = pipe_ctx->top_pipe; in resource_remove_dpp_pipes_for_plane_composition()
3092 if (!pipe_ctx->top_pipe) in resource_remove_dpp_pipes_for_plane_composition()
3354 last_dpp_pipe->bottom_pipe->top_pipe = last_dpp_pipe->top_pipe; in release_dpp_pipe_and_remove_mpc_slice()
[all …]
H A Ddc_hw_sequencer.c324 struct pipe_ctx *top_pipe = pipe_ctx; in get_mpctree_visual_confirm_color() local
326 while (top_pipe->top_pipe) in get_mpctree_visual_confirm_color()
327 top_pipe = top_pipe->top_pipe; in get_mpctree_visual_confirm_color()
329 *color = pipe_colors[top_pipe->pipe_idx]; in get_mpctree_visual_confirm_color()
392 while (top_pipe_ctx->top_pipe != NULL) in get_hdr_visual_confirm_color()
393 top_pipe_ctx = top_pipe_ctx->top_pipe; in get_hdr_visual_confirm_color()
H A Ddc_state.c153 if (cur_pipe->top_pipe) in dc_state_copy_internal()
154 cur_pipe->top_pipe = &dst_state->res_ctx.pipe_ctx[cur_pipe->top_pipe->pipe_idx]; in dc_state_copy_internal()
H A Ddc.c571 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) in dc_stream_forward_crc_window()
637 if (pipe->stream == stream && !pipe->top_pipe && !pipe->prev_odm_pipe) in dc_stream_forward_multiple_crc_window()
1248 if ((context->res_ctx.pipe_ctx[i].top_pipe) && in disable_dangling_plane()
1249 (dc->current_state->res_ctx.pipe_ctx[i].top_pipe)) in disable_dangling_plane()
1250 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe->pipe_idx != in disable_dangling_plane()
1251 dc->current_state->res_ctx.pipe_ctx[i].top_pipe->pipe_idx; in disable_dangling_plane()
1253 pipe_split_change = context->res_ctx.pipe_ctx[i].top_pipe != in disable_dangling_plane()
1254 dc->current_state->res_ctx.pipe_ctx[i].top_pipe; in disable_dangling_plane()
1266 if (old_stream && !dc->current_state->res_ctx.pipe_ctx[i].top_pipe && in disable_dangling_plane()
1542 || ctx->res_ctx.pipe_ctx[i].top_pipe in program_timing_sync()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn30/
H A Ddcn30_resource.c1546 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn30_split_stream_for_mpc_or_odm()
1548 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn30_split_stream_for_mpc_or_odm()
1557 if (!sec_pipe->top_pipe) in dcn30_split_stream_for_mpc_or_odm()
1571 sec_pipe->bottom_pipe->top_pipe = sec_pipe; in dcn30_split_stream_for_mpc_or_odm()
1574 sec_pipe->top_pipe = pri_pipe; in dcn30_split_stream_for_mpc_or_odm()
1739 pipe->top_pipe = NULL; in dcn30_internal_validate_bw()
1746 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn30_internal_validate_bw()
1747 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn30_internal_validate_bw() local
1750 top_pipe->bottom_pipe = bottom_pipe; in dcn30_internal_validate_bw()
1752 bottom_pipe->top_pipe = top_pipe; in dcn30_internal_validate_bw()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn32/
H A Ddcn32_fpu.c1897 if (pri_pipe->top_pipe && pri_pipe->top_pipe->next_odm_pipe) { in dcn32_split_stream_for_mpc_or_odm()
1899 sec_pipe->top_pipe = pri_pipe->top_pipe->next_odm_pipe; in dcn32_split_stream_for_mpc_or_odm()
1907 ASSERT(sec_pipe->top_pipe == NULL); in dcn32_split_stream_for_mpc_or_odm()
1909 if (!sec_pipe->top_pipe) in dcn32_split_stream_for_mpc_or_odm()
1926 sec_pipe->top_pipe = pri_pipe; in dcn32_split_stream_for_mpc_or_odm()
1992 if (pipe->top_pipe) { in dcn32_apply_merge_split_flags_helper()
2000 pipe->top_pipe = NULL; in dcn32_apply_merge_split_flags_helper()
2008 } else if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) { in dcn32_apply_merge_split_flags_helper()
2009 struct pipe_ctx *top_pipe = pipe->top_pipe; in dcn32_apply_merge_split_flags_helper() local
2014 bottom_pipe->top_pipe = top_pipe; in dcn32_apply_merge_split_flags_helper()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn401/
H A Ddcn401_hwseq.c118 if (pipe_ctx->top_pipe == NULL) { in dcn401_program_gamut_remap()
1153 pipe_ctx->top_pipe && in dcn401_set_cursor_position()
1314 const struct pipe_ctx *top_pipe) in dcn401_wait_for_dcc_meta_propagation() argument
1317 const struct pipe_ctx *pipe_ctx = top_pipe; in dcn401_wait_for_dcc_meta_propagation()
1812 if (pipe_ctx->top_pipe == NULL) { in dcn401_reset_back_end_for_pipe()
1848 pipe_ctx->top_pipe = NULL; in dcn401_reset_back_end_for_pipe()
1899 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in dcn401_calculate_vready_offset_for_group()
2137 && !context->res_ctx.pipe_ctx[i].top_pipe in dcn401_program_front_end_for_ctx()
2188 if (pipe->plane_state && !pipe->top_pipe) { in dcn401_program_front_end_for_ctx()
2221 !pipe->top_pipe && in dcn401_program_front_end_for_ctx()
[all …]
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn20/
H A Ddcn20_hwseq.c725 pipe_ctx->top_pipe = NULL; in dcn20_plane_atomic_disable()
847 if (pipe_ctx->top_pipe != NULL) in dcn20_enable_stream_timing()
1027 if (pipe_ctx->top_pipe == NULL in dcn20_set_output_transfer_func()
1363 if (!pipe_ctx->top_pipe in dcn20_enable_plane()
1385 if (!pipe || pipe->top_pipe) in dcn20_pipe_control_lock()
1870 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in dcn20_calculate_vready_offset_for_group()
2190 !pipe->top_pipe && in dcn20_program_front_end_for_ctx()
2498 if (pipe_ctx->top_pipe == NULL) { in dcn20_update_bandwidth()
2698 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
2846 if (pipe_ctx->top_pipe == NULL) { in dcn20_reset_back_end_for_pipe()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn10/
H A Ddcn10_hwseq.c115 if (pipe_ctx->top_pipe || in dcn10_lock_all_pipes()
946 for (other_pipe = pipe->top_pipe; other_pipe != NULL; other_pipe = other_pipe->top_pipe) { in calculate_vready_offset_for_group()
1332 pipe_ctx->top_pipe = NULL; in dcn10_plane_atomic_disable()
1746 if (pipe_ctx_old->top_pipe) in dcn10_reset_hw_ctx_wrap()
1941 if (!pipe || pipe->top_pipe) in dcn10_pipe_control_lock()
2025 if (!pipe || pipe->top_pipe) in dcn10_cursor_lock()
2545 if (!pipe_ctx->top_pipe in dcn10_enable_plane()
2581 if (pipe_ctx->top_pipe) { in dcn10_is_rear_mpo_fix_required()
2584 while (top->top_pipe) in dcn10_is_rear_mpo_fix_required()
3050 if (pipe_ctx->top_pipe || in dcn10_wait_for_pending_cleared()
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/linux-6.15/drivers/gpu/drm/amd/display/dc/link/
H A Dlink_resource.c42 if (pipe->stream && pipe->stream->link && pipe->top_pipe == NULL) { in link_get_cur_link_res()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/calcs/
H A Ddcn_calcs.c312 } else if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) { in pipe_ctx_to_e2e_pipe_params()
545 secondary_pipe->bottom_pipe->top_pipe = secondary_pipe; in split_stream_across_pipes()
548 secondary_pipe->top_pipe = primary_pipe; in split_stream_across_pipes()
899 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1206 if (pipe->top_pipe && pipe->top_pipe->plane_state == pipe->plane_state) in dcn_validate_bandwidth()
1271 hsplit_pipe->bottom_pipe->top_pipe = pipe; in dcn_validate_bandwidth()
1274 hsplit_pipe->top_pipe = NULL; in dcn_validate_bandwidth()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn201/
H A Ddcn201_hwseq.c60 bool sec_split = pipe_ctx->top_pipe && in patch_address_for_sbs_tb_stereo()
61 pipe_ctx->top_pipe->plane_state == pipe_ctx->plane_state; in patch_address_for_sbs_tb_stereo()
534 if (pipe->top_pipe) in dcn201_pipe_control_lock()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/
H A Ddcn20_fpu.c1426 if (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
1428 struct pipe_ctx *first_pipe = res_ctx->pipe_ctx[i].top_pipe; in dcn20_populate_dml_pipes_from_context()
1431 while (first_pipe->top_pipe && first_pipe->top_pipe->plane_state in dcn20_populate_dml_pipes_from_context()
1433 first_pipe = first_pipe->top_pipe; in dcn20_populate_dml_pipes_from_context()
1442 pipes[pipe_cnt].pipe.src.hsplit_grp = res_ctx->pipe_ctx[i].top_pipe->pipe_idx; in dcn20_populate_dml_pipes_from_context()
1594 || (res_ctx->pipe_ctx[i].top_pipe && res_ctx->pipe_ctx[i].top_pipe->plane_state == pln) in dcn20_populate_dml_pipes_from_context()
1663 split_pipe = res_ctx->pipe_ctx[i].top_pipe; in dcn20_populate_dml_pipes_from_context()
1666 split_pipe = split_pipe->top_pipe; in dcn20_populate_dml_pipes_from_context()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn314/
H A Ddcn314_hwseq.c397 if (pipe->top_pipe || pipe->prev_odm_pipe) in dcn314_resync_fifo_dccg_dio()
475 if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) { in apply_symclk_on_tx_off_wa()
/linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/
H A Ddml21_utils.c171 (dc_pipe->top_pipe == NULL || in dml21_populate_mall_allocation_size()
172 dc_pipe->plane_state != dc_pipe->top_pipe->plane_state) && in dml21_populate_mall_allocation_size()
/linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce100/
H A Ddce_clk_mgr.c177 if (pipe_ctx->top_pipe) in dce_get_max_pixel_clock_for_all_paths()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dcn31/
H A Ddcn31_hwseq.c523 ASSERT(!pipe_ctx->top_pipe); in dcn31_reset_back_end_for_pipe()
595 if (pipe_ctx_old->top_pipe || pipe_ctx_old->prev_odm_pipe) in dcn31_reset_hw_ctx_wrap()
/linux-6.15/drivers/gpu/drm/amd/display/dc/hwss/dce110/
H A Ddce110_hwseq.c2270 if (!pipe_ctx_old->stream || pipe_ctx_old->top_pipe) in dce110_reset_hw_ctx_wrap()
2354 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2392 if (pipe_ctx->top_pipe) in dce110_setup_audio_dto()
2446 if (pipe_ctx->stream == NULL || pipe_ctx->top_pipe) in dce110_apply_ctx_to_hw()
2486 if (pipe_ctx->top_pipe || pipe_ctx->prev_odm_pipe) in dce110_apply_ctx_to_hw()
3118 if (pipe_ctx->top_pipe && pipe_ctx->plane_state != pipe_ctx->top_pipe->plane_state) in dce110_set_cursor_position()
/linux-6.15/drivers/gpu/drm/amd/display/dc/inc/
H A Dcore_types.h453 struct pipe_ctx *top_pipe; member
/linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dcn21/
H A Ddcn21_resource.c854 …if (!pipe->top_pipe && !pipe->plane_state && context->bw_ctx.dml.vba.ODMCombineEnabled[pipe_idx]) { in dcn21_fast_validate_bw()
868 if (pipe->top_pipe && pipe->plane_state == pipe->top_pipe->plane_state) in dcn21_fast_validate_bw()

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