Searched refs:reg_ctrl2 (Results 1 – 2 of 2) sorted by relevance
1256 u32 reg_fdcbt, reg_ctrl2; in flexcan_set_bittiming_cbt() local1292 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_set_bittiming_cbt()1298 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_set_bittiming_cbt()1361 u32 reg_ctrl2; in flexcan_ram_init() local1371 reg_ctrl2 = priv->read(®s->ctrl2); in flexcan_ram_init()1372 reg_ctrl2 |= FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init()1373 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()1380 reg_ctrl2 &= ~FLEXCAN_CTRL2_WRMFRZ; in flexcan_ram_init()1381 priv->write(reg_ctrl2, ®s->ctrl2); in flexcan_ram_init()1653 reg_ctrl2 |= FLEXCAN_CTRL2_ECRWRE; in flexcan_chip_start()[all …]
840 u32 reg, reg_ctrl, reg_ctrl2; in dsi_update_dsc_timing() local883 reg_ctrl2 = dsi_read(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2); in dsi_update_dsc_timing()888 reg_ctrl2 &= ~DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH__MASK; in dsi_update_dsc_timing()889 reg_ctrl2 |= DSI_COMMAND_COMPRESSION_MODE_CTRL2_STREAM0_SLICE_WIDTH(dsc->slice_chunk_size); in dsi_update_dsc_timing()892 dsi_write(msm_host, REG_DSI_COMMAND_COMPRESSION_MODE_CTRL2, reg_ctrl2); in dsi_update_dsc_timing()