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Searched refs:regVCN_RB_ENABLE (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dvcn_v5_0_1.c641 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
643 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
652 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start_dpg_mode()
654 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start_dpg_mode()
796 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
798 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
807 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v5_0_1_start()
809 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v5_0_1_start()
H A Dumsch_mm_v4_0.c235 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_start()
237 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_start()
250 data = RREG32_SOC15(VCN, 0, regVCN_RB_ENABLE); in umsch_mm_v4_0_ring_stop()
252 WREG32_SOC15(VCN, 0, regVCN_RB_ENABLE, data); in umsch_mm_v4_0_ring_stop()
H A Dvcn_v5_0_0.c777 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
779 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
788 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v5_0_0_start_dpg_mode()
790 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start_dpg_mode()
933 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
935 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
944 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v5_0_0_start()
946 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v5_0_0_start()
H A Dvcn_v4_0_5.c1006 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
1008 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1017 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_5_start_dpg_mode()
1019 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start_dpg_mode()
1196 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1198 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1207 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
1209 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_5_start()
1214 RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_5_start()
H A Dvcn_v4_0_3.c948 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
950 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
958 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start_dpg_mode()
960 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start_dpg_mode()
1310 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1312 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
1318 tmp = RREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE); in vcn_v4_0_3_start()
1320 WREG32_SOC15(VCN, vcn_inst, regVCN_RB_ENABLE, tmp); in vcn_v4_0_3_start()
H A Dvcn_v4_0.c1105 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1107 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1116 tmp = RREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE); in vcn_v4_0_start_dpg_mode()
1118 WREG32_SOC15(VCN, inst_idx, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start_dpg_mode()
1290 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1292 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
1301 tmp = RREG32_SOC15(VCN, i, regVCN_RB_ENABLE); in vcn_v4_0_start()
1303 WREG32_SOC15(VCN, i, regVCN_RB_ENABLE, tmp); in vcn_v4_0_start()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_5_0_0_offset.h1114 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_5_offset.h1289 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_0_offset.h1334 #define regVCN_RB_ENABLE … macro
H A Dvcn_4_0_3_offset.h1243 #define regVCN_RB_ENABLE … macro