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Searched refs:regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX (Results 1 – 2 of 2) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_11_5_0_offset.h5092 #define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX macro
H A Dgc_12_0_0_offset.h8948 #define regPA_SC_BINNER_DYNAMIC_BATCH_LIMIT_BASE_IDX macro