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Searched refs:regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h6002 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_5_0_offset.h12850 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_5_1_offset.h12829 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_2_1_offset.h5550 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_4_offset.h13916 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_2_offset.h7249 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_2_0_offset.h5551 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_5_offset.h7008 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_4_1_0_offset.h6090 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro
H A Ddcn_3_1_6_offset.h7469 #define regMPCC_OGAM3_MPCC_OGAM_RAMA_END_CNTL1_G … macro