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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5474 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_5_0_offset.h12322 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_5_1_offset.h12301 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_2_1_offset.h5022 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_1_4_offset.h13388 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_1_2_offset.h6721 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_2_0_offset.h5023 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_1_5_offset.h6480 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_4_1_0_offset.h5562 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro
H A Ddcn_3_1_6_offset.h6941 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_R … macro