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Searched refs:regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5472 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_5_0_offset.h12320 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_5_1_offset.h12299 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_2_1_offset.h5020 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_1_4_offset.h13386 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_1_2_offset.h6719 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_2_0_offset.h5021 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_1_5_offset.h6478 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_4_1_0_offset.h5560 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro
H A Ddcn_3_1_6_offset.h6939 #define regMPCC_OGAM0_MPCC_OGAM_RAMA_OFFSET_G … macro