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Searched refs:regMPCC3_MPCC_UPDATE_LOCK_SEL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5312 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_5_0_offset.h12255 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_5_1_offset.h12234 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_2_1_offset.h4886 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_4_offset.h13324 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_2_offset.h6563 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_2_0_offset.h4887 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_5_offset.h6322 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_4_1_0_offset.h5410 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro
H A Ddcn_3_1_6_offset.h6783 #define regMPCC3_MPCC_UPDATE_LOCK_SEL … macro