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Searched refs:regMPCC1_MPCC_TOP_SEL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5234 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_5_0_offset.h12177 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_5_1_offset.h12156 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_2_1_offset.h4808 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_4_offset.h13250 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_2_offset.h6489 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_2_0_offset.h4809 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_5_offset.h6248 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_4_1_0_offset.h5332 #define regMPCC1_MPCC_TOP_SEL … macro
H A Ddcn_3_1_6_offset.h6709 #define regMPCC1_MPCC_TOP_SEL … macro