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Searched refs:regMPCC0_MPCC_SM_CONTROL (Results 1 – 10 of 10) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h5208 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_5_0_offset.h12151 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_5_1_offset.h12130 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_2_1_offset.h4782 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_1_4_offset.h13226 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_1_2_offset.h6465 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_2_0_offset.h4783 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_1_5_offset.h6224 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_4_1_0_offset.h5306 #define regMPCC0_MPCC_SM_CONTROL … macro
H A Ddcn_3_1_6_offset.h6685 #define regMPCC0_MPCC_SM_CONTROL … macro