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Searched refs:regMMSCH_VF_MAILBOX_RESP (Results 1 – 7 of 7) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Djpeg_v4_0.c517 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_start_sriov()
530 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); in jpeg_v4_0_start_sriov()
H A Djpeg_v4_0_3.c320 WREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP, 0); in jpeg_v4_0_3_start_sriov()
331 resp = RREG32_SOC15(VCN, jpeg_inst, regMMSCH_VF_MAILBOX_RESP); in jpeg_v4_0_3_start_sriov()
H A Dvcn_v4_0_3.c1122 WREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP, 0); in vcn_v4_0_3_start_sriov()
1131 resp = RREG32_SOC15(VCN, vcn_inst, regMMSCH_VF_MAILBOX_RESP); in vcn_v4_0_3_start_sriov()
H A Dvcn_v4_0.c1521 WREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP, 0); in vcn_v4_0_start_sriov()
1533 resp = RREG32_SOC15(VCN, 0, regMMSCH_VF_MAILBOX_RESP); in vcn_v4_0_start_sriov()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/vcn/
H A Dvcn_2_6_0_offset.h484 #define regMMSCH_VF_MAILBOX_RESP … macro
H A Dvcn_4_0_0_offset.h1408 #define regMMSCH_VF_MAILBOX_RESP … macro
H A Dvcn_4_0_3_offset.h1319 #define regMMSCH_VF_MAILBOX_RESP … macro