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Searched refs:regDTBCLK_DTO0_PHASE (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h352 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_5_0_offset.h1362 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_5_1_offset.h1341 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_2_1_offset.h206 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_1_4_offset.h1503 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_1_2_offset.h411 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_2_0_offset.h206 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_1_5_offset.h200 #define regDTBCLK_DTO0_PHASE … macro
H A Ddcn_3_1_6_offset.h613 #define regDTBCLK_DTO0_PHASE … macro