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Searched refs:regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_3_6_0_offset.h10917 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_5_0_offset.h9710 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_5_1_offset.h9689 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_2_1_offset.h10079 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_4_offset.h10831 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_2_offset.h10912 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_2_0_offset.h10080 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_5_offset.h10667 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro
H A Ddcn_3_1_6_offset.h11136 #define regDP4_DP_MSA_TIMING_PARAM4_BASE_IDX … macro