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Searched refs:regCP_VMID_RESET (Results 1 – 9 of 9) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c4884 WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe); in gfx_v11_0_soft_reset()
4888 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4889 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4890 RREG32_SOC15(GC, 0, regCP_VMID_RESET); in gfx_v11_0_soft_reset()
4946 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET)) in gfx_v11_0_soft_reset()
H A Dmes_v11_0.c391 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); in mes_v11_0_reset_queue_mmio()
H A Dmes_v12_0.c410 WREG32_SOC15(GC, 0, regCP_VMID_RESET, value); in mes_v12_0_reset_queue_mmio()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_4_2_offset.h569 #define regCP_VMID_RESET … macro
H A Dgc_9_4_3_offset.h3030 #define regCP_VMID_RESET … macro
H A Dgc_11_5_0_offset.h3289 #define regCP_VMID_RESET … macro
H A Dgc_12_0_0_offset.h3600 #define regCP_VMID_RESET … macro
H A Dgc_11_0_0_offset.h4316 #define regCP_VMID_RESET … macro
H A Dgc_11_0_3_offset.h4540 #define regCP_VMID_RESET … macro