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Searched refs:mmCP_RB2_WPTR (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2130 return RREG32(mmCP_RB2_WPTR); in gfx_v6_0_ring_get_wptr()
2151 WREG32(mmCP_RB2_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_compute()
2152 (void)RREG32(mmCP_RB2_WPTR); in gfx_v6_0_ring_set_wptr_compute()
2200 WREG32(mmCP_RB2_WPTR, ring->wptr); in gfx_v6_0_cp_compute_resume()
H A Dgfx_v9_0.c175 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
176 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
H A Dgfx_v10_0.c305 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
306 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB2_WPTR),
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h511 #define mmCP_RB2_WPTR 0x3069 macro
H A Dgfx_7_0_d.h217 #define mmCP_RB2_WPTR 0x3069 macro
H A Dgfx_7_2_d.h217 #define mmCP_RB2_WPTR 0x3069 macro
H A Dgfx_8_0_d.h241 #define mmCP_RB2_WPTR 0x3069 macro
H A Dgfx_8_1_d.h242 #define mmCP_RB2_WPTR 0x3069 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2432 #define mmCP_RB2_WPTR macro
H A Dgc_9_1_offset.h2709 #define mmCP_RB2_WPTR macro
H A Dgc_9_2_1_offset.h2647 #define mmCP_RB2_WPTR macro
H A Dgc_10_1_0_offset.h4773 #define mmCP_RB2_WPTR macro
H A Dgc_10_3_0_offset.h4426 #define mmCP_RB2_WPTR macro