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Searched refs:mmCP_RB0_WPTR (Results 1 – 15 of 15) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v6_0.c2093 WREG32(mmCP_RB0_WPTR, ring->wptr); in gfx_v6_0_cp_gfx_resume()
2126 return RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_get_wptr()
2139 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v6_0_ring_set_wptr_gfx()
2140 (void)RREG32(mmCP_RB0_WPTR); in gfx_v6_0_ring_set_wptr_gfx()
H A Dgfx_v7_0.c2566 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_cp_gfx_resume()
2601 return RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_get_wptr_gfx()
2608 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v7_0_ring_set_wptr_gfx()
2609 (void)RREG32(mmCP_RB0_WPTR); in gfx_v7_0_ring_set_wptr_gfx()
H A Dgfx_v8_0.c4277 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_cp_gfx_resume()
6003 return RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_get_wptr_gfx()
6015 WREG32(mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v8_0_ring_set_wptr_gfx()
6016 (void)RREG32(mmCP_RB0_WPTR); in gfx_v8_0_ring_set_wptr_gfx()
H A Dgfx_v9_0.c170 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
3389 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_cp_gfx_resume()
5335 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v9_0_ring_get_wptr_gfx()
5351 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v9_0_ring_set_wptr_gfx()
H A Dgfx_v10_0.c300 SOC15_REG_ENTRY_STR(GC, 0, mmCP_RB0_WPTR),
6490 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr)); in gfx_v10_0_cp_gfx_resume()
8521 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR); in gfx_v10_0_ring_get_wptr_gfx()
8538 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, in gfx_v10_0_ring_set_wptr_gfx()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_d.h499 #define mmCP_RB0_WPTR 0x3045 macro
H A Dgfx_7_0_d.h214 #define mmCP_RB0_WPTR 0x3045 macro
H A Dgfx_7_2_d.h214 #define mmCP_RB0_WPTR 0x3045 macro
H A Dgfx_8_0_d.h238 #define mmCP_RB0_WPTR 0x3045 macro
H A Dgfx_8_1_d.h239 #define mmCP_RB0_WPTR 0x3045 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2420 #define mmCP_RB0_WPTR … macro
H A Dgc_9_1_offset.h2697 #define mmCP_RB0_WPTR … macro
H A Dgc_9_2_1_offset.h2635 #define mmCP_RB0_WPTR … macro
H A Dgc_10_1_0_offset.h4761 #define mmCP_RB0_WPTR … macro
H A Dgc_10_3_0_offset.h4414 #define mmCP_RB0_WPTR … macro