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Searched refs:mmCP_ME1_PIPE1_INT_CNTL (Results 1 – 13 of 13) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h266 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 macro
H A Dgfx_7_2_d.h268 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 macro
H A Dgfx_8_0_d.h299 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 macro
H A Dgfx_8_1_d.h299 #define mmCP_ME1_PIPE1_INT_CNTL 0x3086 macro
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c5986 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_set_compute_eop_interrupt_state()
6036 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v9_0_get_cpc_int_cntl()
H A Dgfx_v7_0.c4663 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v7_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c5370 return SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_get_cpc_int_cntl()
9090 mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL); in gfx_v10_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6433 mec_int_cntl_reg = mmCP_ME1_PIPE1_INT_CNTL; in gfx_v8_0_set_compute_eop_interrupt_state()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2503 #define mmCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_9_1_offset.h2777 #define mmCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_9_2_1_offset.h2713 #define mmCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_10_1_0_offset.h4843 #define mmCP_ME1_PIPE1_INT_CNTL … macro
H A Dgc_10_3_0_offset.h4502 #define mmCP_ME1_PIPE1_INT_CNTL … macro