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Searched refs:mmCP_HQD_ACTIVE (Results 1 – 19 of 19) sorted by relevance

/linux-6.15/drivers/gpu/drm/amd/pm/powerplay/inc/
H A Dpolaris10_pwrvirus.h1545 { 0x00000000, mmCP_HQD_ACTIVE },
1548 { 0x00000001, mmCP_HQD_ACTIVE },
1550 { 0x00000000, mmCP_HQD_ACTIVE },
1553 { 0x00000001, mmCP_HQD_ACTIVE },
1555 { 0x00000000, mmCP_HQD_ACTIVE },
1558 { 0x00000001, mmCP_HQD_ACTIVE },
1560 { 0x00000000, mmCP_HQD_ACTIVE },
1563 { 0x00000001, mmCP_HQD_ACTIVE },
1565 { 0x00000000, mmCP_HQD_ACTIVE },
1568 { 0x00000001, mmCP_HQD_ACTIVE },
[all …]
/linux-6.15/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_amdkfd_gfx_v7.c197 WREG32(mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
329 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
445 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v9.c294 WREG32_SOC15_RLC(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE, data); in kgd_gfx_v9_hqd_load()
493 act = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_is_occupied()
561 temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_destroy()
1137 if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE)) in kgd_gfx_v9_hqd_get_pq_addr()
1163 uint32_t temp = RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE); in kgd_gfx_v9_hqd_dequeue_wait()
1185 if (!RREG32_SOC15(GC, GET_INST(GC, inst), mmCP_HQD_ACTIVE)) in kgd_gfx_v9_hqd_reset()
H A Damdgpu_amdkfd_gfx_v8.c221 WREG32(mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
361 act = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
480 temp = RREG32(mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
H A Damdgpu_amdkfd_gfx_v10_3.c269 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in hqd_load_v10_3()
468 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_is_occupied_v10_3()
534 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in hqd_destroy_v10_3()
H A Damdgpu_amdkfd_gfx_v10.c283 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, data); in kgd_hqd_load()
482 act = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_is_occupied()
611 temp = RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE); in kgd_hqd_destroy()
H A Dgfx_v9_0.c244 SOC15_REG_ENTRY_STR(GC, 0, mmCP_HQD_ACTIVE),
1034 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_kiq_reset_hw_queue()
3676 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v9_0_kiq_init_register()
3679 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_kiq_init_register()
3758 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, in gfx_v9_0_kiq_init_register()
3773 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v9_0_kiq_fini_register()
3778 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_kiq_fini_register()
3787 WREG32_SOC15_RLC(GC, 0, mmCP_HQD_ACTIVE, 0); in gfx_v9_0_kiq_fini_register()
7277 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v9_0_reset_kcq()
H A Dgfx_v7_0.c2801 if (RREG32(mmCP_HQD_ACTIVE) & 1) { in gfx_v7_0_mqd_deactivate()
2804 if (!(RREG32(mmCP_HQD_ACTIVE) & 1)) in gfx_v7_0_mqd_deactivate()
2959 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v7_0_mqd_commit()
H A Dgfx_v10_0.c3810 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v10_0_kiq_reset_hw_queue()
6992 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0); in gfx_v10_0_kiq_init_register()
6998 if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) { in gfx_v10_0_kiq_init_register()
7001 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v10_0_kiq_init_register()
7084 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, in gfx_v10_0_kiq_init_register()
9583 if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1)) in gfx_v10_0_reset_kcq()
H A Dgfx_v8_0.c4391 if (RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK) { in gfx_v8_0_deactivate_hqd()
4394 if (!(RREG32(mmCP_HQD_ACTIVE) & CP_HQD_ACTIVE__ACTIVE_MASK)) in gfx_v8_0_deactivate_hqd()
4599 for (mqd_reg = mmCP_MQD_BASE_ADDR; mqd_reg <= mmCP_HQD_ACTIVE; mqd_reg++) in gfx_v8_0_mqd_commit()
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_7_0_d.h569 #define mmCP_HQD_ACTIVE 0x3247 macro
H A Dgfx_7_2_d.h582 #define mmCP_HQD_ACTIVE 0x3247 macro
H A Dgfx_8_0_d.h632 #define mmCP_HQD_ACTIVE 0x3247 macro
H A Dgfx_8_1_d.h632 #define mmCP_HQD_ACTIVE 0x3247 macro
/linux-6.15/drivers/gpu/drm/amd/include/asic_reg/gc/
H A Dgc_9_0_offset.h2823 #define mmCP_HQD_ACTIVE … macro
H A Dgc_9_1_offset.h3051 #define mmCP_HQD_ACTIVE … macro
H A Dgc_9_2_1_offset.h3007 #define mmCP_HQD_ACTIVE … macro
H A Dgc_10_1_0_offset.h5307 #define mmCP_HQD_ACTIVE … macro
H A Dgc_10_3_0_offset.h4940 #define mmCP_HQD_ACTIVE … macro