Searched refs:input_clks (Results 1 – 2 of 2) sorted by relevance
392 struct clk *input_clks[WIZ_MAX_INPUT_CLOCKS]; member832 clk = wiz->input_clks[mux_sel->parents[i]]; in wiz_mux_clk_register()1083 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK]); in wiz_clock_init()1108 if (wiz->input_clks[WIZ_CORE_REFCLK1]) { in wiz_clock_init()1109 rate = clk_get_rate(wiz->input_clks[WIZ_CORE_REFCLK1]); in wiz_clock_init()1116 rate = clk_get_rate(wiz->input_clks[WIZ_EXT_REFCLK]); in wiz_clock_init()1138 wiz->input_clks[WIZ_CORE_REFCLK] = clk; in wiz_clock_probe()1146 wiz->input_clks[WIZ_CORE_REFCLK1] = clk; in wiz_clock_probe()1154 wiz->input_clks[WIZ_EXT_REFCLK] = clk; in wiz_clock_probe()
402 struct clk *input_clks[CDNS_SIERRA_INPUT_CLOCKS]; member557 clk_set_rate(phy->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_init()558 clk_set_rate(phy->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_init()1163 sp->input_clks[CMN_REFCLK_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1171 sp->input_clks[CMN_REFCLK1_DIG_DIV] = clk; in cdns_sierra_phy_get_clocks()1187 sp->input_clks[PHY_CLK] = clk; in cdns_sierra_phy_clk()1189 ret = clk_prepare_enable(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_clk()1221 clk_disable_unprepare(sp->input_clks[PHY_CLK]); in cdns_sierra_phy_disable_clocks()1263 clk_set_rate(sp->input_clks[CMN_REFCLK_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()1264 clk_set_rate(sp->input_clks[CMN_REFCLK1_DIG_DIV], 25000000); in cdns_sierra_phy_configure_multilink()