Searched refs:clk_select (Results 1 – 6 of 6) sorted by relevance
37 enum fsl_pwm_clk clk_select; member77 if (a->clk_select != b->clk_select) in fsl_pwm_periodcfg_are_equal()120 rate = clk_get_rate(fpc->clk[fpc->period.clk_select]); in fsl_pwm_ticks_to_ns()148 periodcfg->clk_select = index; in fsl_pwm_calculate_period_clk()260 if (fpc->period.clk_select != periodcfg.clk_select) { in fsl_pwm_apply_config()262 enum fsl_pwm_clk oldclk = fpc->period.clk_select; in fsl_pwm_apply_config()263 enum fsl_pwm_clk newclk = periodcfg.clk_select; in fsl_pwm_apply_config()277 FTM_SC_CLK(periodcfg.clk_select)); in fsl_pwm_apply_config()325 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_apply()488 clk_disable_unprepare(fpc->clk[fpc->period.clk_select]); in fsl_pwm_suspend()[all …]
1059 enum smu_clk_type clk_select = 0; in smu_v11_0_display_clock_voltage_request() local1066 clk_select = SMU_DCEFCLK; in smu_v11_0_display_clock_voltage_request()1069 clk_select = SMU_DISPCLK; in smu_v11_0_display_clock_voltage_request()1072 clk_select = SMU_PIXCLK; in smu_v11_0_display_clock_voltage_request()1075 clk_select = SMU_PHYCLK; in smu_v11_0_display_clock_voltage_request()1078 clk_select = SMU_UCLK; in smu_v11_0_display_clock_voltage_request()1089 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) in smu_v11_0_display_clock_voltage_request()1092 ret = smu_v11_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v11_0_display_clock_voltage_request()1094 if(clk_select == SMU_UCLK) in smu_v11_0_display_clock_voltage_request()
1083 enum smu_clk_type clk_select = 0; in smu_v13_0_display_clock_voltage_request() local1090 clk_select = SMU_DCEFCLK; in smu_v13_0_display_clock_voltage_request()1093 clk_select = SMU_DISPCLK; in smu_v13_0_display_clock_voltage_request()1096 clk_select = SMU_PIXCLK; in smu_v13_0_display_clock_voltage_request()1099 clk_select = SMU_PHYCLK; in smu_v13_0_display_clock_voltage_request()1102 clk_select = SMU_UCLK; in smu_v13_0_display_clock_voltage_request()1113 if (clk_select == SMU_UCLK && smu->disable_uclk_switch) in smu_v13_0_display_clock_voltage_request()1116 ret = smu_v13_0_set_hard_freq_limited_range(smu, clk_select, clk_freq, 0); in smu_v13_0_display_clock_voltage_request()1118 if (clk_select == SMU_UCLK) in smu_v13_0_display_clock_voltage_request()
1580 PPCLK_e clk_select = 0; in vega12_display_clock_voltage_request() local1586 clk_select = PPCLK_DCEFCLK; in vega12_display_clock_voltage_request()1589 clk_select = PPCLK_DISPCLK; in vega12_display_clock_voltage_request()1592 clk_select = PPCLK_PIXCLK; in vega12_display_clock_voltage_request()1595 clk_select = PPCLK_PHYCLK; in vega12_display_clock_voltage_request()1604 clk_request = (clk_select << 16) | clk_freq; in vega12_display_clock_voltage_request()
2305 PPCLK_e clk_select = 0; in vega20_display_clock_voltage_request() local2311 clk_select = PPCLK_DCEFCLK; in vega20_display_clock_voltage_request()2314 clk_select = PPCLK_DISPCLK; in vega20_display_clock_voltage_request()2317 clk_select = PPCLK_PIXCLK; in vega20_display_clock_voltage_request()2320 clk_select = PPCLK_PHYCLK; in vega20_display_clock_voltage_request()2329 clk_request = (clk_select << 16) | clk_freq; in vega20_display_clock_voltage_request()
4043 DSPCLK_e clk_select = 0; in vega10_display_clock_voltage_request() local4048 clk_select = DSPCLK_DCEFCLK; in vega10_display_clock_voltage_request()4051 clk_select = DSPCLK_DISPCLK; in vega10_display_clock_voltage_request()4054 clk_select = DSPCLK_PIXCLK; in vega10_display_clock_voltage_request()4057 clk_select = DSPCLK_PHYCLK; in vega10_display_clock_voltage_request()4066 clk_request = (clk_freq << 16) | clk_select; in vega10_display_clock_voltage_request()