| /linux-6.15/drivers/net/wireless/broadcom/brcm80211/brcmutil/ |
| H A D | d11.c | 30 switch (bw) { in d11n_bw()
43 if (ch->bw == BRCMU_CHAN_BW_20) in brcmu_d11n_encchspec()
52 0, d11n_bw(ch->bw)); in brcmu_d11n_encchspec()
62 switch (bw) { in d11ac_bw()
87 0, d11ac_bw(ch->bw)); in brcmu_d11ac_encchspec()
105 ch->bw = BRCMU_CHAN_BW_20; in brcmu_d11n_decchspec()
109 ch->bw = BRCMU_CHAN_BW_40; in brcmu_d11n_decchspec()
146 ch->bw = BRCMU_CHAN_BW_20; in brcmu_d11ac_decchspec()
150 ch->bw = BRCMU_CHAN_BW_40; in brcmu_d11ac_decchspec()
163 ch->bw = BRCMU_CHAN_BW_80; in brcmu_d11ac_decchspec()
[all …]
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| /linux-6.15/net/ipv4/ |
| H A D | tcp_bbr.c | 258 u64 rate = bw; in bbr_bw_to_pacing_rate()
270 u64 bw; in bbr_init_pacing_rate_from_rtt() local
562 u32 inflight, bw; in bbr_is_next_cycle_phase() local
677 bbr->lt_bw = bw; in bbr_lt_bw_interval_done()
693 u64 bw; in bbr_lt_bw_sampling() local
756 do_div(bw, t); in bbr_lt_bw_sampling()
765 u64 bw; in bbr_update_bw() local
800 minmax_running_max(&bbr->bw, bbr_bw_rtts, bbr->rtt_cnt, bw); in bbr_update_bw()
1030 u32 bw; in bbr_main() local
1034 bw = bbr_bw(sk); in bbr_main()
[all …]
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| /linux-6.15/drivers/net/wireless/intel/iwlwifi/mld/ |
| H A D | tlc.c | 264 enum IWL_TLC_MCS_PER_BW bw, in iwl_mld_set_eht_mcs() argument
279 switch (bw) { in iwl_mld_get_eht_mcs_of_bw()
281 return &eht_mcs->bw._80; in iwl_mld_get_eht_mcs_of_bw()
283 return &eht_mcs->bw._160; in iwl_mld_get_eht_mcs_of_bw()
285 return &eht_mcs->bw._320; in iwl_mld_get_eht_mcs_of_bw()
319 enum IWL_TLC_MCS_PER_BW bw; in iwl_mld_fill_eht_rates() local
355 bw = IWL_TLC_MCS_PER_BW_80; in iwl_mld_fill_eht_rates()
356 iwl_mld_set_eht_mcs(cmd->ht_rates, bw, in iwl_mld_fill_eht_rates()
359 iwl_mld_set_eht_mcs(cmd->ht_rates, bw, in iwl_mld_fill_eht_rates()
362 iwl_mld_set_eht_mcs(cmd->ht_rates, bw, in iwl_mld_fill_eht_rates()
[all …]
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| /linux-6.15/drivers/net/wireless/intel/iwlwifi/mvm/ |
| H A D | rs-fw.c | 257 enum IWL_TLC_MCS_PER_BW bw, in rs_fw_set_eht_mcs_nss() argument
272 switch (bw) { in rs_fw_rs_mcs2eht_mcs()
274 return &eht_mcs->bw._80; in rs_fw_rs_mcs2eht_mcs()
276 return &eht_mcs->bw._160; in rs_fw_rs_mcs2eht_mcs()
278 return &eht_mcs->bw._320; in rs_fw_rs_mcs2eht_mcs()
298 enum IWL_TLC_MCS_PER_BW bw; in rs_fw_eht_set_enabled_rates() local
326 bw = IWL_TLC_MCS_PER_BW_80; in rs_fw_eht_set_enabled_rates()
327 rs_fw_set_eht_mcs_nss(cmd->ht_rates, bw, in rs_fw_eht_set_enabled_rates()
337 for (bw = IWL_TLC_MCS_PER_BW_160; bw <= IWL_TLC_MCS_PER_BW_320; bw++) { in rs_fw_eht_set_enabled_rates()
339 rs_fw_rs_mcs2eht_mcs(bw, eht_rx_mcs); in rs_fw_eht_set_enabled_rates()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/core/ |
| H A D | dc_debug.c | 191 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
192 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
193 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
194 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz, in context_clock_trace()
195 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
196 context->bw_ctx.bw.dcn.clk.socclk_khz); in context_clock_trace()
199 context->bw_ctx.bw.dcn.clk.dispclk_khz, in context_clock_trace()
200 context->bw_ctx.bw.dcn.clk.dppclk_khz, in context_clock_trace()
201 context->bw_ctx.bw.dcn.clk.dcfclk_khz, in context_clock_trace()
203 context->bw_ctx.bw.dcn.clk.fclk_khz, in context_clock_trace()
[all …]
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| /linux-6.15/drivers/gpu/drm/i915/display/ |
| H A D | intel_bw.c | 444 int ct, bw; in icl_get_bw_info() local
546 int ct, bw; in tgl_get_bw_info() local
641 i915->display.bw.max[0].deratedbw[i] = in xe2_hpd_get_bw_info()
643 i915->display.bw.max[0].peakbw[i] = bw; in xe2_hpd_get_bw_info()
647 i915->display.bw.max[0].peakbw[i]); in xe2_hpd_get_bw_info()
651 i915->display.bw.max[0].num_planes = 1; in xe2_hpd_get_bw_info()
654 memcpy(&i915->display.bw.max[i], &i915->display.bw.max[0], in xe2_hpd_get_bw_info()
655 sizeof(i915->display.bw.max[0])); in xe2_hpd_get_bw_info()
679 &dev_priv->display.bw.max[i]; in icl_max_bw_index()
707 &dev_priv->display.bw.max[i]; in tgl_max_bw_index()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/ |
| H A D | dml2_utils.c | 185 context->bw_ctx.bw.dcn.clk.dcfclk_khz = out_clks->dcfclk_khz; in dml2_copy_clocks_to_dc_state()
187 context->bw_ctx.bw.dcn.clk.fclk_khz = out_clks->fclk_khz; in dml2_copy_clocks_to_dc_state()
188 context->bw_ctx.bw.dcn.clk.phyclk_khz = out_clks->phyclk_khz; in dml2_copy_clocks_to_dc_state()
286 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml2_calculate_rq_and_dlg_params()
336 …if (context->bw_ctx.bw.dcn.clk.dppclk_khz < context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res… in dml2_calculate_rq_and_dlg_params()
337 …context->bw_ctx.bw.dcn.clk.dppclk_khz = context->res_ctx.pipe_ctx[dc_pipe_ctx_index].plane_res.bw.… in dml2_calculate_rq_and_dlg_params()
361 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml2_calculate_rq_and_dlg_params()
362 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml2_calculate_rq_and_dlg_params()
370 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz; in dml2_calculate_rq_and_dlg_params()
371 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz ; in dml2_calculate_rq_and_dlg_params()
[all …]
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| /linux-6.15/drivers/net/wireless/ath/ath12k/ |
| H A D | reg.c | 509 u16 bw; in ath12k_reg_adjust_bw() local
511 bw = end_freq - start_freq; in ath12k_reg_adjust_bw()
512 bw = min_t(u16, bw, max_bw); in ath12k_reg_adjust_bw()
514 if (bw >= 80 && bw < 160) in ath12k_reg_adjust_bw()
515 bw = 80; in ath12k_reg_adjust_bw()
516 else if (bw >= 40 && bw < 80) in ath12k_reg_adjust_bw()
517 bw = 40; in ath12k_reg_adjust_bw()
518 else if (bw < 40) in ath12k_reg_adjust_bw()
519 bw = 20; in ath12k_reg_adjust_bw()
521 return bw; in ath12k_reg_adjust_bw()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn30/ |
| H A D | dcn30_fpu.c | 295 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching || in dcn30_fpu_update_soc_for_wm_a()
318 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = false; in dcn30_fpu_calculate_wm_and_dlg()
329 context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching = in dcn30_fpu_calculate_wm_and_dlg()
332 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
369 …context->bw_ctx.bw.dcn.watermarks.b.urgent_ns = get_wm_urgent(&context->bw_ctx.dml, pipes, pipe_cn… in dcn30_fpu_calculate_wm_and_dlg()
422 if (!context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching) { in dcn30_fpu_calculate_wm_and_dlg()
452 context->bw_ctx.bw.dcn.watermarks.a = context->bw_ctx.bw.dcn.watermarks.c; in dcn30_fpu_calculate_wm_and_dlg()
453 context->bw_ctx.bw.dcn.watermarks.a.cstate_pstate.pstate_change_ns = 0; in dcn30_fpu_calculate_wm_and_dlg()
475 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn30_fpu_calculate_wm_and_dlg()
497 if (context->bw_ctx.bw.dcn.clk.fw_based_mclk_switching && in dcn30_fpu_calculate_wm_and_dlg()
[all …]
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| /linux-6.15/drivers/media/dvb-frontends/ |
| H A D | dib7000m.c | 320 if (!bw) in dib7000m_set_bandwidth()
321 bw = 8000; in dib7000m_set_bandwidth()
324 state->current_bandwidth = bw; in dib7000m_set_bandwidth()
394 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000m_reset_pll() local
398 reg_907 = (bw->pll_bypass << 15) | (bw->modulo << 7) | in dib7000m_reset_pll()
399 (bw->ADClkSrc << 6) | (bw->IO_CLK_en_core << 5) | (bw->bypclk_div << 2) | in dib7000m_reset_pll()
401 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset; in dib7000m_reset_pll()
427 const struct dibx000_bandwidth_config *bw = state->cfg.bw; in dib7000mc_reset_pll() local
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
436 (bw->IO_CLK_en_core << 10) | (bw->bypclk_div << 5) | (bw->enable_refdiv << 4) | in dib7000mc_reset_pll()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml2/dml21/ |
| H A D | dml21_wrapper.c | 134 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dml21_calculate_rq_and_dlg_params()
142 context->bw_ctx.bw.dcn.mall_ss_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
143 context->bw_ctx.bw.dcn.mall_ss_psr_active_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
144 context->bw_ctx.bw.dcn.mall_subvp_size_bytes = 0; in dml21_calculate_rq_and_dlg_params()
178 memcpy(&context->bw_ctx.bw.dcn.mcache_allocations[dml_phantom_prog_idx], in dml21_calculate_rq_and_dlg_params()
187 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dml21_calculate_rq_and_dlg_params()
188 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dml21_calculate_rq_and_dlg_params()
190 context->bw_ctx.bw.dcn.clk.max_supported_dispclk_khz = in dml21_calculate_rq_and_dlg_params()
197 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dml21_calculate_rq_and_dlg_params()
205 …context->bw_ctx.bw.dcn.clk.num_ways = dc->res_pool->funcs->calculate_mall_ways_from_bytes(dc, cont… in dml21_calculate_rq_and_dlg_params()
[all …]
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| H A D | dml21_utils.c | 177 context->bw_ctx.bw.dcn.mall_ss_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
181 context->bw_ctx.bw.dcn.mall_subvp_size_bytes += dc_pipe->surface_size_in_mall_bytes; in dml21_populate_mall_allocation_size()
230 pipe_ctx->plane_res.bw.dppclk_khz = pln_prog->min_clocks.dcn4x.dppclk_khz; in dml21_program_dc_pipe()
231 if (context->bw_ctx.bw.dcn.clk.dppclk_khz < pipe_ctx->plane_res.bw.dppclk_khz) in dml21_program_dc_pipe()
232 context->bw_ctx.bw.dcn.clk.dppclk_khz = pipe_ctx->plane_res.bw.dppclk_khz; in dml21_program_dc_pipe()
385 …memset(&context->bw_ctx.bw.dcn.fams2_stream_base_params, 0, sizeof(union dmub_cmd_fams2_config) * … in dml21_build_fams2_programming()
386 …memset(&context->bw_ctx.bw.dcn.fams2_stream_sub_params, 0, sizeof(union dmub_cmd_fams2_config) * D… in dml21_build_fams2_programming()
387 …memset(&context->bw_ctx.bw.dcn.fams2_global_config, 0, sizeof(struct dmub_cmd_fams2_global_config)… in dml21_build_fams2_programming()
495 memcpy(&context->bw_ctx.bw.dcn.fams2_global_config, in dml21_build_fams2_programming()
499 context->bw_ctx.bw.dcn.fams2_global_config.num_streams = num_fams2_streams; in dml21_build_fams2_programming()
[all …]
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| /linux-6.15/drivers/net/wireless/ath/ath11k/ |
| H A D | reg.c | 502 u16 bw; in ath11k_reg_adjust_bw() local
508 bw = min_t(u16, bw, max_bw); in ath11k_reg_adjust_bw()
510 if (bw >= 80 && bw < 160) in ath11k_reg_adjust_bw()
511 bw = 80; in ath11k_reg_adjust_bw()
512 else if (bw >= 40 && bw < 80) in ath11k_reg_adjust_bw()
513 bw = 40; in ath11k_reg_adjust_bw()
514 else if (bw >= 20 && bw < 40) in ath11k_reg_adjust_bw()
515 bw = 20; in ath11k_reg_adjust_bw()
517 bw = 0; in ath11k_reg_adjust_bw()
519 return bw; in ath11k_reg_adjust_bw()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn31/ |
| H A D | dcn31_fpu.c | 533 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
534 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
535 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn31_calculate_wm_and_dlg_fp()
561 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn31_calculate_wm_and_dlg_fp()
565 context->bw_ctx.bw.dcn.clk.socclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
566 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
567 context->bw_ctx.bw.dcn.clk.dcfclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
568 context->bw_ctx.bw.dcn.clk.dcfclk_deep_sleep_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
569 context->bw_ctx.bw.dcn.clk.dramclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
570 context->bw_ctx.bw.dcn.clk.fclk_khz = 0; in dcn31_calculate_wm_and_dlg_fp()
[all …]
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| /linux-6.15/drivers/media/usb/dvb-usb-v2/ |
| H A D | mxl111sf-tuner.c | 79 u8 bw) in mxl111sf_calc_phy_tune_regs() argument
84 switch (bw) { in mxl111sf_calc_phy_tune_regs()
193 mxl_dbg("(freq = %d, bw = 0x%x)", freq, bw); in mxl1x1sf_tune_rf()
206 reg_ctrl_array = mxl111sf_calc_phy_tune_regs(freq, bw); in mxl1x1sf_tune_rf()
268 u8 bw; in mxl111sf_tuner_set_params() local
275 bw = 0; /* ATSC */ in mxl111sf_tuner_set_params()
278 bw = 1; /* US CABLE */ in mxl111sf_tuner_set_params()
283 bw = 6; in mxl111sf_tuner_set_params()
286 bw = 7; in mxl111sf_tuner_set_params()
289 bw = 8; in mxl111sf_tuner_set_params()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce112/ |
| H A D | dce112_resource.c | 903 &context->bw_ctx.bw.dce)) in dce112_validate_bandwidth()
911 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce112_validate_bandwidth()
912 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce112_validate_bandwidth()
928 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce112_validate_bandwidth()
929 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce112_validate_bandwidth()
944 context->bw_ctx.bw.dce.stutter_mode_enable, in dce112_validate_bandwidth()
948 context->bw_ctx.bw.dce.all_displays_in_sync, in dce112_validate_bandwidth()
949 context->bw_ctx.bw.dce.dispclk_khz, in dce112_validate_bandwidth()
950 context->bw_ctx.bw.dce.sclk_khz, in dce112_validate_bandwidth()
951 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce112_validate_bandwidth()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/clk_mgr/dce110/ |
| H A D | dce110_clk_mgr.c | 183 context->bw_ctx.bw.dce.all_displays_in_sync; in dce11_pplib_apply_display_requirements()
185 context->bw_ctx.bw.dce.nbp_state_change_enable == false; in dce11_pplib_apply_display_requirements()
187 context->bw_ctx.bw.dce.cpuc_state_change_enable == false; in dce11_pplib_apply_display_requirements()
189 context->bw_ctx.bw.dce.cpup_state_change_enable == false; in dce11_pplib_apply_display_requirements()
191 context->bw_ctx.bw.dce.blackout_recovery_time_us; in dce11_pplib_apply_display_requirements()
205 pp_display_cfg->min_memory_clock_khz = context->bw_ctx.bw.dce.yclk_khz in dce11_pplib_apply_display_requirements()
211 context->bw_ctx.bw.dce.sclk_khz); in dce11_pplib_apply_display_requirements()
224 = context->bw_ctx.bw.dce.sclk_deep_sleep_khz; in dce11_pplib_apply_display_requirements()
255 int patched_disp_clk = context->bw_ctx.bw.dce.dispclk_khz; in dce11_update_clocks()
270 context->bw_ctx.bw.dce.dispclk_khz = dce_set_clock(clk_mgr_base, patched_disp_clk); in dce11_update_clocks()
|
| /linux-6.15/drivers/net/wireless/realtek/rtw88/ |
| H A D | phy.c | 1700 u8 bw; in rtw_xref_txpwr_lmt_by_bw() local
1702 for (bw = RTW_CHANNEL_WIDTH_20; bw <= RTW_CHANNEL_WIDTH_40; bw++) in rtw_xref_txpwr_lmt_by_bw()
1732 u8 bw, rs; in rtw_cfg_txpwr_lmt_by_alt() local
1734 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) in rtw_cfg_txpwr_lmt_by_alt()
1737 bw, rs); in rtw_cfg_txpwr_lmt_by_alt()
2173 bw = min_t(u8, bw, RTW_CHANNEL_WIDTH_40); in rtw_phy_get_tx_power_limit()
2294 u8 bw; in rtw_phy_set_tx_power_index_by_rs() local
2306 bw, ch, regd); in rtw_phy_set_tx_power_index_by_rs()
2400 u8 regd, bw, rs; in rtw_phy_tx_power_limit_config() local
2406 for (bw = 0; bw < RTW_CHANNEL_WIDTH_MAX; bw++) in rtw_phy_tx_power_limit_config()
[all …]
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| /linux-6.15/Documentation/netlink/specs/ |
| H A D | net_shaper.yaml | 84 doc: Metric used by the given shaper for bw-min, bw-max and burst.
86 name: bw-min
90 name: bw-max
171 doc: The device accepts 'bps' metric for bw-min, bw-max and burst.
175 doc: The device accepts 'pps' metric for bw-min, bw-max and burst.
225 - bw-min
226 - bw-max
256 - bw-min
257 - bw-max
319 - bw-min
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calcs.c | 630 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a;
631 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a;
634 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a;
1153 context->bw_ctx.bw.dcn.watermarks.b = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1154 context->bw_ctx.bw.dcn.watermarks.c = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1155 context->bw_ctx.bw.dcn.watermarks.d = context->bw_ctx.bw.dcn.watermarks.a; in dcn_validate_bandwidth()
1169 if (context->bw_ctx.bw.dcn.clk.dispclk_khz < in dcn_validate_bandwidth()
1171 context->bw_ctx.bw.dcn.clk.dispclk_khz = in dcn_validate_bandwidth()
1175 context->bw_ctx.bw.dcn.clk.dppclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz / in dcn_validate_bandwidth()
1180 context->bw_ctx.bw.dcn.clk.max_supported_dppclk_khz = in dcn_validate_bandwidth()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/resource/dce110/ |
| H A D | dce110_resource.c | 980 &context->bw_ctx.bw.dce)) in dce110_validate_bandwidth()
990 if (memcmp(&dc->current_state->bw_ctx.bw.dce, in dce110_validate_bandwidth()
991 &context->bw_ctx.bw.dce, sizeof(context->bw_ctx.bw.dce))) { in dce110_validate_bandwidth()
1007 context->bw_ctx.bw.dce.urgent_wm_ns[0].b_mark, in dce110_validate_bandwidth()
1008 context->bw_ctx.bw.dce.urgent_wm_ns[0].a_mark, in dce110_validate_bandwidth()
1023 context->bw_ctx.bw.dce.stutter_mode_enable, in dce110_validate_bandwidth()
1027 context->bw_ctx.bw.dce.all_displays_in_sync, in dce110_validate_bandwidth()
1028 context->bw_ctx.bw.dce.dispclk_khz, in dce110_validate_bandwidth()
1029 context->bw_ctx.bw.dce.sclk_khz, in dce110_validate_bandwidth()
1030 context->bw_ctx.bw.dce.sclk_deep_sleep_khz, in dce110_validate_bandwidth()
[all …]
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| /linux-6.15/net/wireless/ |
| H A D | util.c | 1457 switch (rate->bw) { in cfg80211_calculate_bitrate_vht()
1485 rate->bw, rate->mcs, rate->nss); in cfg80211_calculate_bitrate_vht()
1529 if (rate->bw == RATE_INFO_BW_160 || in cfg80211_calculate_bitrate_he()
1534 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1538 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1542 (rate->bw == RATE_INFO_BW_HE_RU && in cfg80211_calculate_bitrate_he()
1556 rate->bw, rate->he_ru_alloc); in cfg80211_calculate_bitrate_he()
1630 if (rate->bw == RATE_INFO_BW_320 || in cfg80211_calculate_bitrate_eht()
1774 switch (rate->bw) { in cfg80211_calculate_bitrate_s1g()
1809 rate->bw, rate->mcs, rate->nss); in cfg80211_calculate_bitrate_s1g()
[all …]
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| /linux-6.15/drivers/gpu/drm/amd/display/dc/dml/dcn20/ |
| H A D | dcn20_fpu.c | 1160 context->bw_ctx.bw.dcn.clk.dramclk_khz = dc->debug.min_dram_clk_khz; in dcn20_calculate_dlg_params()
1164 context->bw_ctx.bw.dcn.clk.p_state_change_support = in dcn20_calculate_dlg_params()
1171 …context->bw_ctx.bw.dcn.clk.p_state_change_support |= context->bw_ctx.bw.dcn.clk.fw_based_mclk_swit… in dcn20_calculate_dlg_params()
1173 context->bw_ctx.bw.dcn.clk.dppclk_khz = 0; in dcn20_calculate_dlg_params()
1178 context->bw_ctx.bw.dcn.clk.dispclk_khz = dc->debug.min_disp_clk_khz; in dcn20_calculate_dlg_params()
1201 context->res_ctx.pipe_ctx[i].plane_res.bw.dppclk_khz = in dcn20_calculate_dlg_params()
1214 context->bw_ctx.bw.dcn.clk.p_state_change_support = true; in dcn20_calculate_dlg_params()
1217 context->bw_ctx.bw.dcn.clk.bw_dppclk_khz = context->bw_ctx.bw.dcn.clk.dppclk_khz; in dcn20_calculate_dlg_params()
1218 context->bw_ctx.bw.dcn.clk.bw_dispclk_khz = context->bw_ctx.bw.dcn.clk.dispclk_khz; in dcn20_calculate_dlg_params()
1242 context->bw_ctx.bw.dcn.clk.p_state_change_support, in dcn20_calculate_dlg_params()
[all …]
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| /linux-6.15/include/net/ |
| H A D | regulatory.h | 225 #define REG_RULE_EXT(start, end, bw, gain, eirp, dfs_cac, reg_flags) \ argument
229 .freq_range.max_bandwidth_khz = MHZ_TO_KHZ(bw), \
236 #define REG_RULE(start, end, bw, gain, eirp, reg_flags) \ argument
237 REG_RULE_EXT(start, end, bw, gain, eirp, 0, reg_flags)
|
| /linux-6.15/arch/x86/include/asm/shared/ |
| H A D | io.h | 7 #define BUILDIO(bwl, bw, type) \ argument
10 asm volatile("out" #bwl " %" #bw "0, %w1" \
17 asm volatile("in" #bwl " %w1, %" #bw "0" \
|