Searched refs:SSE (Results 1 – 10 of 10) sorted by relevance
| /linux-6.15/arch/x86/kernel/ |
| H A D | verify_cpu.S | 128 jz .Lverify_cpu_no_longmode # only try to force SSE on AMD
131 btr $15,%eax # enable SSE
|
| /linux-6.15/Documentation/devicetree/bindings/arm/ |
| H A D | arm,corstone1000.yaml | 14 ARM's Corstone1000 includes pre-verified Corstone SSE-710 subsystem that
|
| /linux-6.15/drivers/scsi/aic7xxx/ |
| H A D | aic7xxx_pci.c | 591 #define SSE 0x40 macro
1942 if (status1 & SSE) { in ahc_pci_intr()
1963 if ((status1 & (DPE|SSE|RMA|RTA|STA|DPR)) == 0) { in ahc_pci_intr()
|
| H A D | aic79xx.reg | 1144 field SSE 0x40
1162 field SSE 0x40
1179 field SSE 0x40
1195 field SSE 0x40
1212 field SSE 0x40
1227 field SSE 0x40
1244 field SSE 0x40
|
| H A D | aic79xx_pci.c | 730 #define SSE 0x40 macro
|
| H A D | aic79xx_reg.h_shipped | 1309 #define SSE 0x40
|
| /linux-6.15/arch/x86/crypto/ |
| H A D | chacha-ssse3-x86_64.S | 231 # the state matrix in SSE registers four times. As we need some scratch
236 # which allows us to do XOR in SSE registers. 8/16-bit word rotation is
|
| /linux-6.15/tools/arch/x86/kcpuid/ |
| H A D | cpuid.csv | 87 1, 0, edx, 25, sse , SSE instructions
650 0x80000001, 0, ecx, 7, misalignsse , Misaligned SSE mode
871 0x8000001a, 0, eax, 1, movu_preferred , SSE: MOVU* better than MOVL*/MOVH*
872 0x8000001a, 0, eax, 2, fp_256 , internal FP/SSE exec data path is…
|
| /linux-6.15/arch/x86/ |
| H A D | Kconfig.cpu | 228 of SSE and tells gcc to treat the CPU as a 686.
|
| /linux-6.15/ |
| H A D | CREDITS | 1826 D: Pentium III FXSR, SSE support
|