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Searched refs:SM (Results 1 – 25 of 74) sorted by relevance

123

/linux-6.15/drivers/net/wireless/ath/ath9k/
H A Dar9003_aic.c184 SM(37, AR_PHY_AIC_F_WLAN) | in ar9003_aic_cal_start()
188 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
195 SM(0, AR_PHY_AIC_ENABLE))); in ar9003_aic_cal_start()
203 SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9003_aic_cal_start()
204 SM(0, AR_PHY_AIC_RSSI_MIN))); in ar9003_aic_cal_start()
207 (SM(15, AR_PHY_AIC_RSSI_MAX) | in ar9003_aic_cal_start()
420 SM(sram.vga_quad_sign, in ar9003_aic_cal_post_process()
422 SM(sram.com_att_6db, in ar9003_aic_cal_post_process()
424 SM(sram.valid, in ar9003_aic_cal_post_process()
426 SM(sram.rot_dir_att_db, in ar9003_aic_cal_post_process()
[all …]
H A Dar9003_rtt.c77 val = SM(data28, AR_PHY_RTT_SW_RTT_TABLE_DATA); in ar9003_hw_rtt_load_hist_entry()
80 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_load_hist_entry()
81 SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_load_hist_entry()
82 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_load_hist_entry()
86 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_load_hist_entry()
95 val &= ~SM(1, AR_PHY_RTT_SW_RTT_TABLE_WRITE); in ar9003_hw_rtt_load_hist_entry()
146 val = SM(0, AR_PHY_RTT_SW_RTT_TABLE_ACCESS) | in ar9003_hw_rtt_fill_hist_entry()
147 SM(0, AR_PHY_RTT_SW_RTT_TABLE_WRITE) | in ar9003_hw_rtt_fill_hist_entry()
148 SM(index, AR_PHY_RTT_SW_RTT_TABLE_ADDR); in ar9003_hw_rtt_fill_hist_entry()
153 val |= SM(1, AR_PHY_RTT_SW_RTT_TABLE_ACCESS); in ar9003_hw_rtt_fill_hist_entry()
H A Dbtcoex.c86 SM(ath_bt_config.wl_active_time, AR_BT_WL_ACTIVE_TIME) | in ath9k_hw_init_btcoex_hw()
87 SM(ath_bt_config.wl_qc_time, AR_BT_WL_QC_TIME); in ath9k_hw_init_btcoex_hw()
96 SM(time_extend, AR_BT_TIME_EXTEND) | in ath9k_hw_init_btcoex_hw()
99 SM(ath_bt_config.bt_mode, AR_BT_MODE) | in ath9k_hw_init_btcoex_hw()
100 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) | in ath9k_hw_init_btcoex_hw()
101 SM(rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) | in ath9k_hw_init_btcoex_hw()
103 SM(first_slot_time, AR_BT_FIRST_SLOT_TIME) | in ath9k_hw_init_btcoex_hw()
104 SM(qnum, AR_BT_QCU_THRESH); in ath9k_hw_init_btcoex_hw()
108 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | in ath9k_hw_init_btcoex_hw()
275 SM(bt_weight, AR_BTCOEX_BT_WGHT) | in ath9k_hw_btcoex_set_weight()
[all …]
H A Dar9003_mci.c868 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
869 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
870 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
873 SM(0, AR_BTCOEX_CTRL_1_CHAIN_ACK) | in ar9003_mci_set_btcoex_ctrl_9565_1ANT()
887 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
888 SM(0, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
889 SM(0, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9565_2ANT()
906 SM(1, AR_BTCOEX_CTRL_WBTIMER_EN) | in ar9003_mci_set_btcoex_ctrl_9462()
907 SM(1, AR_BTCOEX_CTRL_PA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9462()
908 SM(1, AR_BTCOEX_CTRL_LNA_SHARED) | in ar9003_mci_set_btcoex_ctrl_9462()
[all …]
H A Dar9002_phy.c239 SM(SPUR_RSSI_THRESH, AR_PHY_SPUR_REG_SPUR_RSSI_THRESH)); in ar9002_hw_spur_mitigate()
268 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar9002_hw_spur_mitigate()
269 SM(spur_delta_phase, AR_PHY_TIMING11_SPUR_DELTA_PHASE)); in ar9002_hw_spur_mitigate()
320 pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); in ar9002_hw_compute_pll_control()
321 pll |= SM(pll_div, AR_RTC_9160_PLL_DIV); in ar9002_hw_compute_pll_control()
324 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
326 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9002_hw_compute_pll_control()
462 regval |= SM(antdiv_ctrl1, AR_PHY_9285_ANT_DIV_CTL); in ar9002_hw_set_bt_ant_diversity()
463 regval |= SM(antdiv_ctrl2, AR_PHY_9285_ANT_DIV_ALT_LNACONF); in ar9002_hw_set_bt_ant_diversity()
465 regval |= SM((antdiv_ctrl1 >> 1), AR_PHY_9285_ANT_DIV_ALT_GAINTB); in ar9002_hw_set_bt_ant_diversity()
[all …]
H A Deeprom_9287.c443 regval = SM(pdGainOverlap_t2, in ath9k_hw_set_ar9287_power_cal_table()
445 | SM(gainBoundaries[0], in ath9k_hw_set_ar9287_power_cal_table()
447 | SM(gainBoundaries[1], in ath9k_hw_set_ar9287_power_cal_table()
449 | SM(gainBoundaries[2], in ath9k_hw_set_ar9287_power_cal_table()
451 | SM(gainBoundaries[3], in ath9k_hw_set_ar9287_power_cal_table()
872 SM(pModal->iqCalICh[i], in ath9k_hw_ar9287_set_board_values()
874 SM(pModal->iqCalQCh[i], in ath9k_hw_ar9287_set_board_values()
926 SM(pModal->db2, AR9287_AN_RF2G3_DB2) | in ath9k_hw_ar9287_set_board_values()
927 SM(pModal->ob_cck, AR9287_AN_RF2G3_OB_CCK) | in ath9k_hw_ar9287_set_board_values()
928 SM(pModal->ob_psk, AR9287_AN_RF2G3_OB_PSK) | in ath9k_hw_ar9287_set_board_values()
[all …]
H A Dmac.c33 SM(ah->txok_interrupt_mask, AR_IMR_S0_QCU_TXOK) in ath9k_hw_set_txq_interrupts()
36 SM(ah->txerr_interrupt_mask, AR_IMR_S1_QCU_TXERR) in ath9k_hw_set_txq_interrupts()
391 SM(cwMin, AR_D_LCL_IFS_CWMIN) | in ath9k_hw_resettxqueue()
392 SM(qi->tqi_cwmax, AR_D_LCL_IFS_CWMAX) | in ath9k_hw_resettxqueue()
393 SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
424 SM(qi->tqi_burstTime, AR_D_CHNTIME_DUR) | in ath9k_hw_resettxqueue()
464 | SM(0, AR_D_LCL_IFS_CWMAX) in ath9k_hw_resettxqueue()
465 | SM(qi->tqi_aifs, AR_D_LCL_IFS_AIFS)); in ath9k_hw_resettxqueue()
499 SM(AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL, in ath9k_hw_resettxqueue()
1037 filter = SM(set, AR_D_TXBLK_WRITE_COMMAND); in ath9k_hw_set_tx_filter()
[all …]
H A Dar9002_mac.c227 ctl6 = SM(i->keytype, AR_EncrType); in ar9002_set_txdesc()
243 | SM(0, AR_BurstDur)); in ar9002_set_txdesc()
261 ctl1 |= (i->keyix != ATH9K_TXKEYIX_INVALID ? SM(i->keyix, AR_DestIdx) : 0) in ar9002_set_txdesc()
262 | SM(i->type, AR_FrameType) in ar9002_set_txdesc()
269 ctl6 |= SM(i->aggr_len, AR_AggrLen); in ar9002_set_txdesc()
273 ctl6 |= SM(i->ndelim, AR_PadDelim); in ar9002_set_txdesc()
284 | SM(i->txpower[0], AR_XmitPower0) in ar9002_set_txdesc()
309 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9002_set_txdesc()
311 WRITE_ONCE(ads->ds_ctl9, SM(i->txpower[1], AR_XmitPower1)); in ar9002_set_txdesc()
312 WRITE_ONCE(ads->ds_ctl10, SM(i->txpower[2], AR_XmitPower2)); in ar9002_set_txdesc()
[all …]
H A Dar5008_phy.c484 SM(spur_freq_sd, AR_PHY_TIMING11_SPUR_FREQ_SD) | in ar5008_hw_spur_mitigate()
918 pll = SM(0x5, AR_RTC_9160_PLL_REFDIV); in ar9160_hw_compute_pll_control()
921 pll |= SM(0x1, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
923 pll |= SM(0x2, AR_RTC_9160_PLL_CLKSEL); in ar9160_hw_compute_pll_control()
926 pll |= SM(0x50, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
928 pll |= SM(0x58, AR_RTC_9160_PLL_DIV); in ar9160_hw_compute_pll_control()
941 pll |= SM(0x1, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
943 pll |= SM(0x2, AR_RTC_PLL_CLKSEL); in ar5008_hw_compute_pll_control()
946 pll |= SM(0xa, AR_RTC_PLL_DIV); in ar5008_hw_compute_pll_control()
948 pll |= SM(0xb, AR_RTC_PLL_DIV); in ar5008_hw_compute_pll_control()
[all …]
H A Dar9003_mac.c74 | SM(0, AR_BurstDur)); in ar9003_set_txdesc()
90 ctl17 = SM(i->keytype, AR_EncrType); in ar9003_set_txdesc()
104 | SM(i->txpower[0], AR_XmitPower0) in ar9003_set_txdesc()
113 SM(i->keyix, AR_DestIdx) : 0) in ar9003_set_txdesc()
114 | SM(i->type, AR_FrameType) in ar9003_set_txdesc()
122 ctl17 |= SM(i->aggr_len, AR_AggrLen); in ar9003_set_txdesc()
126 ctl17 |= SM(i->ndelim, AR_PadDelim); in ar9003_set_txdesc()
136 ctl12 |= SM(val, AR_PAPRDChainMask); in ar9003_set_txdesc()
152 | SM(i->rtscts_rate, AR_RTSCTSRate)); in ar9003_set_txdesc()
156 WRITE_ONCE(ads->ctl20, SM(i->txpower[1], AR_XmitPower1)); in ar9003_set_txdesc()
[all …]
H A Deeprom_4k.c347 SM(pdGainOverlap_t2, in ath9k_hw_set_4k_power_cal_table()
349 | SM(gainBoundaries[0], in ath9k_hw_set_4k_power_cal_table()
351 | SM(gainBoundaries[1], in ath9k_hw_set_4k_power_cal_table()
353 | SM(gainBoundaries[2], in ath9k_hw_set_4k_power_cal_table()
355 | SM(gainBoundaries[3], in ath9k_hw_set_4k_power_cal_table()
785 regVal |= SM(ant_div_control1, in ath9k_hw_4k_set_board_values()
787 regVal |= SM(ant_div_control2, in ath9k_hw_4k_set_board_values()
789 regVal |= SM((ant_div_control2 >> 2), in ath9k_hw_4k_set_board_values()
791 regVal |= SM((ant_div_control1 >> 1), in ath9k_hw_4k_set_board_values()
793 regVal |= SM((ant_div_control1 >> 2), in ath9k_hw_4k_set_board_values()
[all …]
H A Deeprom_def.c440 SM(pModal-> bswMargin[i], AR_PHY_GAIN_2GHZ_BSW_MARGIN), in ath9k_hw_def_set_gain()
443 SM(pModal->bswAtten[i], AR_PHY_GAIN_2GHZ_BSW_ATTEN), in ath9k_hw_def_set_gain()
457 SM(txRxAttenLocal, AR_PHY_RXGAIN_TXRX_ATTEN), in ath9k_hw_def_set_gain()
460 SM(pModal->rxTxMarginCh[i], AR_PHY_GAIN_2GHZ_RXTX_MARGIN), in ath9k_hw_def_set_gain()
499 SM(pModal->iqCalICh[i], in ath9k_hw_def_set_board_values()
501 SM(pModal->iqCalQCh[i], in ath9k_hw_def_set_board_values()
569 | SM(pModal->txEndToXpaOff, in ath9k_hw_def_set_board_values()
571 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
573 | SM(pModal->txFrameToXpaOn, in ath9k_hw_def_set_board_values()
875 SM(0x6, in ath9k_hw_set_def_power_cal_table()
[all …]
H A Dar9003_phy.c581 pll = SM(0x5, AR_RTC_9300_SOC_PLL_REFDIV); in ar9003_hw_compute_pll_control_soc()
584 pll |= SM(0x1, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
586 pll |= SM(0x2, AR_RTC_9300_SOC_PLL_CLKSEL); in ar9003_hw_compute_pll_control_soc()
588 pll |= SM(0x2c, AR_RTC_9300_SOC_PLL_DIV_INT); in ar9003_hw_compute_pll_control_soc()
598 pll = SM(0x5, AR_RTC_9300_PLL_REFDIV); in ar9003_hw_compute_pll_control()
601 pll |= SM(0x1, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
603 pll |= SM(0x2, AR_RTC_9300_PLL_CLKSEL); in ar9003_hw_compute_pll_control()
605 pll |= SM(0x2c, AR_RTC_9300_PLL_DIV); in ar9003_hw_compute_pll_control()
1453 radar_0 |= SM(conf->fir_power, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_set_radar_params()
2006 val |= SM(0x7f, AR_PHY_RADAR_0_FIRPWR); in ar9003_hw_bb_watchdog_check()
[all …]
/linux-6.15/Documentation/devicetree/bindings/arm/samsung/
H A Dsamsung-boards.yaml79 - samsung,t311 # Samsung Galaxy Tab 3 8.0 3G (SM-T311)
80 - samsung,t315 # Samsung Galaxy Tab 3 8.0 LTE (SM-T315)
153 - samsung,chagall-wifi # Samsung SM-T800
154 - samsung,klimt-wifi # Samsung SM-T700
184 - samsung,k3g # Samsung Galaxy S5 (SM-G900H)
230 - samsung,dreamlte # Samsung Galaxy S8 (SM-G950F)
236 - samsung,starlte # Samsung Galaxy S9 (SM-G960F)
242 - samsung,c1s # Samsung Galaxy Note20 5G (SM-N981B)
243 - samsung,r8s # Samsung Galaxy S20 FE (SM-G780F)
244 - samsung,x1s # Samsung Galaxy S20 5G (SM-G981B)
[all …]
/linux-6.15/drivers/net/wireless/ath/ath6kl/
H A Dhif.c213 SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
216 ~SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_rx_control()
577 SM(INT_STATUS_ENABLE_ERROR, 0x01) | in ath6kl_hif_enable_intrs()
578 SM(INT_STATUS_ENABLE_CPU, 0x01) | in ath6kl_hif_enable_intrs()
579 SM(INT_STATUS_ENABLE_COUNTER, 0x01); in ath6kl_hif_enable_intrs()
585 dev->irq_en_reg.int_status_en |= SM(INT_STATUS_ENABLE_MBOX_DATA, 0x01); in ath6kl_hif_enable_intrs()
592 SM(ERROR_STATUS_ENABLE_RX_UNDERFLOW, 0x01) | in ath6kl_hif_enable_intrs()
593 SM(ERROR_STATUS_ENABLE_TX_OVERFLOW, 0x1); in ath6kl_hif_enable_intrs()
599 dev->irq_en_reg.cntr_int_status_en = SM(COUNTER_INT_STATUS_ENABLE_BIT, in ath6kl_hif_enable_intrs()
/linux-6.15/drivers/net/wireless/ath/ath10k/
H A Dhw.c676 slottime = SM(slottime, WAVE1_PCU_GBL_IFS_SLOT); in ath10k_hw_qca988x_set_coverage_class()
683 ack_timeout = SM(ack_timeout, WAVE1_PCU_ACK_CTS_TIMEOUT_ACK); in ath10k_hw_qca988x_set_coverage_class()
779 reg_val |= (SM(hw_clk->rnfrac, BB_PLL_CONFIG_FRAC) | in ath10k_hw_qca6174_enable_pll_clock()
780 SM(hw_clk->outdiv, BB_PLL_CONFIG_OUTDIV)); in ath10k_hw_qca6174_enable_pll_clock()
792 reg_val |= SM(hw_clk->settle_time, WLAN_PLL_SETTLE_TIME); in ath10k_hw_qca6174_enable_pll_clock()
804 reg_val |= SM(1, SOC_CORE_CLK_CTRL_DIV); in ath10k_hw_qca6174_enable_pll_clock()
822 reg_val |= (SM(hw_clk->refdiv, WLAN_PLL_CONTROL_REFDIV) | in ath10k_hw_qca6174_enable_pll_clock()
823 SM(hw_clk->div, WLAN_PLL_CONTROL_DIV) | in ath10k_hw_qca6174_enable_pll_clock()
824 SM(1, WLAN_PLL_CONTROL_NOPWD)); in ath10k_hw_qca6174_enable_pll_clock()
855 reg_val |= SM(0, WLAN_PLL_CONTROL_BYPASS); in ath10k_hw_qca6174_enable_pll_clock()
[all …]
H A Dhtt_tx.c34 return SM(exp, HTT_TX_Q_STATE_ENTRY_EXP) | in ath10k_htt_tx_txq_calc_size()
35 SM(factor, HTT_TX_Q_STATE_ENTRY_FACTOR); in ath10k_htt_tx_txq_calc_size()
702 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_32()
764 info |= SM(htt->tx_q_state.type, in ath10k_htt_send_frag_desc_bank_cfg_64()
1303 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_hl()
1306 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_hl()
1319 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); in ath10k_htt_tx_hl()
1476 flags0 |= SM(txmode, HTT_DATA_TX_DESC_FLAGS0_PKT_TYPE); in ath10k_htt_tx_32()
1479 flags0 |= SM(ATH10K_HW_TXRX_MGMT, in ath10k_htt_tx_32()
1514 flags1 |= SM((u16)tid, HTT_DATA_TX_DESC_FLAGS1_EXT_TID); in ath10k_htt_tx_32()
[all …]
/linux-6.15/Documentation/devicetree/bindings/display/
H A Dsm501fb.txt1 * SM SM501
3 The SM SM501 is a LCD controller, with proper hardware, it can also
/linux-6.15/arch/m68k/fpsp040/
H A Ddecbin.S31 | adds and muls in FP0. Set the sign according to SM.
40 | added if SM = 1 and subtracted if SM = 0. Scale the
43 | SM = 0 a non-zero digit in the integer position
44 | SM = 1 a non-zero digit in Mant0, lsd of the fraction
435 bfextu %d4{#0:#2},%d0 | {FPCR[6],FPCR[5],SM,SE}
/linux-6.15/drivers/iio/chemical/
H A DKconfig20 tristate "Atlas Scientific OEM SM sensors"
28 Atlas Scientific OEM SM sensors:
29 * pH SM sensor
30 * EC SM sensor
31 * ORP SM sensor
/linux-6.15/arch/arm64/boot/dts/exynos/
H A Dexynos9810-starlte.dts3 * Samsung Galaxy S9 (starlte/SM-G960F) device tree source
15 model = "Samsung Galaxy S9 (SM-G960F)";
/linux-6.15/arch/arm64/boot/dts/qcom/
H A Dmsm8216-samsung-fortuna3g.dts8 model = "Samsung Galaxy Grand Prime (SM-G530H)";
H A Dmsm8916-samsung-j3ltetw.dts8 model = "Samsung Galaxy J3 (2016) (SM-J320YZ)";
/linux-6.15/drivers/firmware/arm_scmi/vendors/imx/
H A Dimx95.rst12 The System Manager (SM) is a low-level system function which runs on a System
16 underlying features of the hardware. The primary purpose of the SM is to allow
20 clients. This allows the SM to provide access control, arbitration, and
23 SM introduces a concept Logic Machine(LM) which is analogous to VM and each has
30 port, and deploy the SM on supported processors.
32 The SM implements an interface compliant with the Arm SCMI Specification
443 settings/actions that must be exposed from the SM to agents. They are device
445 control modules, IOMUX_GPR, and other GPR/CSR owned by the SM. This protocol
452 - Obtain platform (i.e. SM) build information.
/linux-6.15/arch/arm64/boot/dts/ti/
H A Dk3-am6548-iot2050-advanced-sm.dts10 * AM6548-based (quad-core) IOT2050 SM variant, Product Generation 2
24 model = "SIMATIC IOT2050 Advanced SM";

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