| /linux-6.15/include/dt-bindings/clock/ |
| H A D | rk3036-cru.h | 23 #define SCLK_UART0 77 macro
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| H A D | exynos7-clk.h | 79 #define SCLK_UART0 2 macro
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| H A D | s5pv210.h | 197 #define SCLK_UART0 175 macro
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| H A D | rk3188-cru-common.h | 20 #define SCLK_UART0 64 macro
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| H A D | rk3128-cru.h | 25 #define SCLK_UART0 77 macro
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| H A D | rk3228-cru.h | 24 #define SCLK_UART0 77 macro
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| H A D | rk3308-cru.h | 21 #define SCLK_UART0 17 macro
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| H A D | rv1108-cru.h | 22 #define SCLK_UART0 72 macro
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| H A D | rk3328-cru.h | 27 #define SCLK_UART0 38 macro
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| H A D | rk3288-cru.h | 32 #define SCLK_UART0 77 macro
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| H A D | rk3368-cru.h | 30 #define SCLK_UART0 77 macro
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| H A D | rockchip,rk3528-cru.h | 31 #define SCLK_UART0 19 macro
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| H A D | rockchip,rk3576-cru.h | 158 #define SCLK_UART0 140 macro
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| H A D | rockchip,rv1126-cru.h | 82 #define SCLK_UART0 16 macro
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| H A D | rk3399-cru.h | 38 #define SCLK_UART0 81 macro
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| H A D | rockchip,rk3588-cru.h | 682 #define SCLK_UART0 667 macro
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| H A D | rk3568-cru.h | 24 #define SCLK_UART0 11 macro
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| /linux-6.15/Documentation/devicetree/bindings/clock/ |
| H A D | rockchip,rk3528-cru.yaml | 14 controller for SoC peripherals. For example, it provides SCLK_UART0 and
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| /linux-6.15/drivers/clk/rockchip/ |
| H A D | clk-rk3036.c | 150 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3128.c | 186 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| H A D | clk-rk3228.c | 200 MUX(SCLK_UART0, "sclk_uart0", mux_uart0_p, CLK_SET_RATE_PARENT,
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| /linux-6.15/drivers/clk/samsung/ |
| H A D | clk-s5pv210.c | 599 GATE(SCLK_UART0, "sclk_uart0", "dout_uart0", CLK_SRC_MASK0, 12,
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| /linux-6.15/arch/arm/boot/dts/rockchip/ |
| H A D | rk3xxx.dtsi | 114 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| /linux-6.15/arch/arm64/boot/dts/rockchip/ |
| H A D | rk3528.dtsi | 375 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
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| /linux-6.15/arch/arm/boot/dts/samsung/ |
| H A D | s5pv210.dtsi | 322 <&clocks SCLK_UART0>;
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