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Searched refs:RGMII (Results 1 – 25 of 92) sorted by relevance

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/linux-6.15/Documentation/devicetree/bindings/net/
H A Dmotorcomm,yt8xxx.yaml23 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
32 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
58 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
75 The YT8531 RGMII LDO voltage supports 1.8V/3.3V, and the LDO voltage can
97 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
103 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
109 Use original or inverted RGMII Transmit PHY Clock to drive the RGMII
H A Dxlnx,gmii-to-rgmii.yaml7 title: Xilinx GMII to RGMII Converter
14 Independent Interface (RGMII) core provides the RGMII between RGMII-compliant
H A Dadi,adin.yaml21 RGMII RX Clock Delay used only when PHY operates in RGMII mode with
28 RGMII TX Clock Delay used only when PHY operates in RGMII mode with
H A Dmediatek-dwmac.yaml85 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
89 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple of 290,
95 For MT2712 RGMII interface, Allowed value need to be a multiple of 170,
99 For MT8188/MT8195 RGMII/RMII/MII interface, Allowed value need to be a multiple
118 1. tx clock will be inversed in MII/RGMII case,
128 1. rx clock will be inversed in MII/RGMII case.
H A Dibm,emac.txt5 special McMAL DMA controller, and sometimes an RGMII or ZMII
55 - rgmii-device : 1 cell, required iff connected to an RGMII. phandle
56 of the RGMII device node.
58 - rgmii-channel : 1 cell, required iff connected to an RGMII. Which
59 RGMII channel is used by this EMAC.
195 iv) RGMII node
203 - revision : as provided by the RGMII new version register if
H A Dingenic,mac.yaml44 description: RGMII receive clock delay defined in pico seconds
47 description: RGMII transmit clock delay defined in pico seconds
H A Dti,dp83869.yaml21 This device interfaces to the MAC layer through Reduced GMII (RGMII) and
24 conversions. The DP83869HM can also support Bridge Conversion from RGMII to
25 SGMII and SGMII to RGMII.
H A Dti,dp83867.yaml25 Media Independent Interface (GMII) or Reduced GMII (RGMII).
81 RGMII Receive Clock Delay - see dt-bindings/net/ti-dp83867.h
88 RGMII Transmit Clock Delay - see dt-bindings/net/ti-dp83867.h
95 PHY_INTERFACE_MODE_RGMII, by default, does not behave as RGMII with no
H A Dapm-xgene-enet.txt8 - "apm,xgene-enet": RGMII based 1G interface
42 - tx-delay: Delay value for RGMII bridge TX clock.
46 - rx-delay: Delay value for RGMII bridge RX clock.
H A Dallwinner,sun8i-a83t-emac.yaml85 External RGMII PHY TX clock delay chain value in ps.
93 External RGMII PHY TX clock delay chain value in ps.
110 External RGMII PHY TX clock delay chain value in ps.
H A Dcavium-pip.txt40 - rx-delay: Delay value for RGMII receive clock. Optional. Disabled if 0.
43 - tx-delay: Delay value for RGMII transmit clock. Optional. Disabled if 0.
H A Dfsl,fec.yaml104 RGMII TXC clock or RMII reference clock. It depends on board design,
105 the clock is required if RGMII TXC and RMII reference clock source from
109 The "enet_2x_txclk"(option), for RGMII sampling clock which fixed at 250Mhz.
110 The clock is required if SoC RGMII enable clock delay.
H A Dethernet-controller.yaml276 RGMII Receive Clock Delay defined in pico seconds. This is used for
281 RGMII Transmit Clock Delay defined in pico seconds. This is used for
294 # The RGMII specification requires a 2ns delay between the data and
295 # clock signals on the RGMII bus. How this delay is implemented is not
317 # any RGMII phy mode other than 'rgmii-id' is probably wrong, and is
340 # Experience to date is that all PHYs which implement RGMII also
H A Dqca,ar803x.yaml65 RGMII I/O voltage regulator (see regulator/regulator.yaml).
67 The PHY supports RGMII I/O voltages of 1.5V, 1.8V and 2.5V. You can
H A Damlogic,meson-dwmac.yaml64 The internal RGMII TX clock delay (provided by this driver)
81 The internal RGMII RX clock delay in nanoseconds. Deprecated, use
/linux-6.15/Documentation/devicetree/bindings/clock/
H A Dstarfive,jh7110-aoncrg.yaml23 - description: GMAC0 RMII reference or GMAC0 RGMII RX
30 - description: GMAC0 RMII reference or GMAC0 RGMII RX
31 - description: STG AXI/AHB or GMAC0 RGMII RX
39 - description: GMAC0 RGMII RX
H A Dstarfive,jh7110-syscrg.yaml23 - description: GMAC1 RMII reference or GMAC1 RGMII RX
37 - description: GMAC1 RGMII RX
/linux-6.15/include/dt-bindings/phy/
H A Dphy-lan966x-serdes.h10 #define RGMII(x) (SERDES6G_MAX + 1 + (x)) macro
11 #define RGMII_MAX RGMII(2)
/linux-6.15/Documentation/devicetree/bindings/phy/
H A Dmicrochip,lan966x-serdes.yaml14 3 SERDES6G and 2 RGMII interfaces. Two of the SERDES6G support QSGMII.
20 following macros are defined CU(X), SERDES6G(X), RGMII(X). Where X is a
H A Dti,phy-gmii-sel.yaml15 two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
36 | | | RGMII <------->
/linux-6.15/Documentation/devicetree/bindings/net/pcs/
H A Drenesas,rzn1-miic.yaml14 responsible to do MII passthrough or convert it to RMII/RGMII.
35 - description: RGMII reference clock
/linux-6.15/arch/arm64/boot/dts/freescale/
H A Dfsl-lx2160a-bluebox3-rev-a.dts15 /* The RGMII PHYs have a different MDIO address */
/linux-6.15/arch/arm64/boot/dts/amlogic/
H A Dmeson-gxm-vega-s96.dts28 /* External PHY is in RGMII */
/linux-6.15/drivers/phy/microchip/
H A Dlan966x_serdes.c101 SERDES_MUX_RGMII(RGMII(0), 2, HSIO_HW_CFG_RGMII_0_CFG |
107 SERDES_MUX_RGMII(RGMII(1), 3, HSIO_HW_CFG_RGMII_1_CFG |
113 SERDES_MUX_RGMII(RGMII(0), 5, HSIO_HW_CFG_RGMII_0_CFG |
119 SERDES_MUX_RGMII(RGMII(1), 6, HSIO_HW_CFG_RGMII_1_CFG |
/linux-6.15/arch/powerpc/boot/dts/
H A Dkmeter1.dts314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
457 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
464 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */

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