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Searched refs:REG_TEST_FLD (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_btrs.c138 if (!REG_TEST_FLD(VPU_HW_BTRS_LNL_TILE_FUSE, VALID, fuse)) { in read_tile_config_fuse()
558 return REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, READY, val) && in ivpu_hw_btrs_is_idle()
559 REG_TEST_FLD(VPU_HW_BTRS_MTL_VPU_STATUS, IDLE, val); in ivpu_hw_btrs_is_idle()
563 return REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, READY, val) && in ivpu_hw_btrs_is_idle()
564 REG_TEST_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, IDLE, val); in ivpu_hw_btrs_is_idle()
834 if (REG_TEST_FLD(VPU_HW_BTRS_MTL_INTERRUPT_STAT, ATS_ERR, reg)) in diagnose_failure_mtl()
857 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI0_ERR, reg)) in diagnose_failure_lnl()
860 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, CFI1_ERR, reg)) in diagnose_failure_lnl()
863 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR0_ERR, reg)) in diagnose_failure_lnl()
868 if (REG_TEST_FLD(VPU_HW_BTRS_LNL_INTERRUPT_STAT, IMR1_ERR, reg)) in diagnose_failure_lnl()
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H A Divpu_hw_ip.c1026 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) in diagnose_failure_37xx()
1043 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, reg)) in diagnose_failure_40xx()
1092 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1095 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, HOST_IPC_FIFO_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1098 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1101 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1110 if (REG_TEST_FLD(VPU_37XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT, status)) in ivpu_hw_ip_irq_handler_37xx()
1126 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) in ivpu_hw_ip_irq_handler_40xx()
1132 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) in ivpu_hw_ip_irq_handler_40xx()
1135 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) in ivpu_hw_ip_irq_handler_40xx()
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H A Divpu_mmu.c997 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1000 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_PRIQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1003 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_EVTQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1006 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, MSI_CMDQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1009 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, PRIQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1012 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, EVTQ_ABT, active)) in ivpu_mmu_irq_gerr_handler()
1015 if (REG_TEST_FLD(IVPU_MMU_REG_GERROR, CMDQ, active)) in ivpu_mmu_irq_gerr_handler()
H A Divpu_hw_reg_io.h44 #define REG_TEST_FLD(REG, FLD, val) \ macro