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Searched refs:REG_CLR_FLD (Results 1 – 4 of 4) sorted by relevance

/linux-6.15/drivers/accel/ivpu/
H A Divpu_hw_ip.c235 val = REG_CLR_FLD(VPU_37XX_HOST_SS_AON_VPU_IDLE_GEN, EN, val); in idle_gen_drive_37xx()
247 val = REG_CLR_FLD(VPU_40XX_HOST_SS_AON_IDLE_GEN, EN, val); in idle_gen_drive_40xx()
404 val = REG_CLR_FLD(VPU_37XX_HOST_SS_CPR_CLK_SET, TOP_NOC, val); in host_ss_clk_drive_37xx()
421 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, TOP_NOC, val); in host_ss_clk_drive_40xx()
422 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, DSS_MAS, val); in host_ss_clk_drive_40xx()
423 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_CLK_EN, CSS_MAS, val); in host_ss_clk_drive_40xx()
468 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, TOP_NOC, val); in host_ss_rst_drive_40xx()
469 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, DSS_MAS, val); in host_ss_rst_drive_40xx()
470 val = REG_CLR_FLD(VPU_40XX_HOST_SS_CPR_RST_EN, CSS_MAS, val); in host_ss_rst_drive_40xx()
546 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in top_noc_qreqn_drive_40xx()
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H A Divpu_hw_btrs.c376 val = REG_CLR_FLD(VPU_HW_BTRS_MTL_VPU_D0I3_CONTROL, I3, val); in d0i3_drive_mtl()
401 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_D0I3_CONTROL, I3, val); in d0i3_drive_lnl()
527 val = REG_CLR_FLD(VPU_HW_BTRS_LNL_VPU_STATUS, PERF_CLK, val); in ivpu_hw_btrs_profiling_freq_reg_set_lnl()
H A Divpu_hw_reg_io.h38 #define REG_CLR_FLD(REG, FLD, val) \ macro
H A Divpu_mmu.c880 val = REG_CLR_FLD(IVPU_MMU_REG_CR0, EVTQEN, val); in ivpu_mmu_evtq_set()